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Synchronous to Asynchronous Conversion

A Case Study: The Blowfish Algorithm Implementation
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Part of the IFIP — The International Federation for Information Processing book series (IFIPAICT, volume 34)

Abstract

This work introduces a novel methodology that eases the synchronous to asynchronous conversion of existing digital circuits. Synchronous single-phased circuits may have its performance improved with the use of a variable rate clock generator if the conversion is done on some key circuits. This methodology is used to improve the performance of a soft-core implementation of the Blowfish cryptographic algorithm.

Key words

Asynchronous logic cryptography VLSI 

References

  1. [i]
    Barbosa, V., Gafni, E. “Concurrency in heavily loaded neighborhood-constrained systems”. ACM Transactions on Prog. Languages and Systems, vol 11, no. 4, Oct 1989.Google Scholar
  2. [ii]
    Barbosa, V. C., “An Introduction to Distributed Algorithms ”, MIT Press, 1996.Google Scholar
  3. [iii]
    Dijkstra, E. “Cooperating Sequential Processes” In Programming Languages, F. Genuys, Academic Press, New York, 1968, pp 43–112.Google Scholar
  4. [iv]
    Meng, T. “Synchronization design for digital systems” Kluwer Academic, 1991.Google Scholar
  5. [v]
    Jou, S. and Chuang I. “Low-Power Globally Asynchronous Locally Synchronous DesignGoogle Scholar
  6. [vi]
    Using Self-Timed Circuit Technology“ IEEE Intl Symp. on Circuits and Systems. Hong Kong, June 1997.Google Scholar
  7. [vi]
    França F., Alves V., Granja E. — Edge Reversal Based Asynchronous Timing Scheme — International Symposyum on Circuits and Systems, Monterey, USA, 1998.Google Scholar
  8. [Vii]
    França F., Alves V., Granja E. — A Multi phase Asynchronous Timing Scheme — SBCCI, Gramado, Brazil, 1997.Google Scholar
  9. [viii]
    Viii]Alves V., França F., Granja E. — A BIST Scheme for Asynchronous Logic — Asian Test Symposium, Singapore, 1998.Google Scholar
  10. [ix]
    França, F., Alves, V., Granja, E.- Patent Reg INPI BR Google Scholar
  11. [x]
    Franklin, M., Pan T. “Performance Comparison of Asynchronous Adders” in Intl Symp. on Advanced Research in Asynchronous Circuits and Systems. November 1994.Google Scholar
  12. [xi]
    Schneier, B.- Description of a New Variable-Length Key, 64-bit Block Cipher (Blowfish) Cambridge Security Workshop Proceedings,Springer-Verlag, Dec 1993.Google Scholar
  13. [xii]
    Schneier, B. —Applied Cryptography— John Wiley and Sons, New York, 1996.Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2000

Authors and Affiliations

  1. 1.COPPE — Federal University of Rio de JaneiroRioBrazil
  2. 2.IME — Military Institute of EngineeringRioBrazil

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