Abstract
Symbolic Trajectory Evaluation (STE) is a model checking algorithm that mixes the use of lattice structures with binary decision diagrams. In addition to this algorithmic decision procedure for the logic, there is also a sound and complete set of inference rules for the logic. Together, these make STE an attractive candidate for a verification system. In this talk we will briefly introduce the underlying theory of STE. We will then discuss the challenges we faced in making STE the basic model checker in the Voss hardware verification system and how the inference rules were used to extend the capabilities of the system. The emphasis of the talk will be on the process of taking a nice theory and making it practically useful.
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© 1998 Springer Science+Business Media Dordrecht
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Seger, C. (1998). From Lattices to Practical Formal Hardware Verification. In: Gries, D., de Roever, WP. (eds) Programming Concepts and Methods PROCOMET ’98. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35358-6_2
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DOI: https://doi.org/10.1007/978-0-387-35358-6_2
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