Abstract
A silicon compiler, Balsa-c, has been developed for the automatic synthesis of asynchronous, delay-insensitive circuits from the language Balsa. Balsa is derived from CSP with similar language constructs and a single-bit granularity type system.
Balsa compiles to intermediate handshake circuits by an extended form of the compilation function used in the Tangram system. The handshake circuits are subsequently mapped to CMOS implementations of 4-phase bundled-data asynchronous circuits by a suite of parameterised component-generating scripts within the Cadence design framework.
Chapter PDF
Similar content being viewed by others
References
Barringer, H., Fellows, D., Gough, G., links, P., Marsden, B., Williams, A. (1996), A Framework for Asynchronous Micropipeline Circuits. in Proceedings of European Simulation Symposium (ESS’ 96) — Genoa Italy
Hoare, C. (1995) Communicating Sequential Processes,Prentice-Hall
Berkel, K., Rem M. (1993), VLSI Programming of Asynchronous Circuits for Low Power. in `Asynchronous Digital Circuit Design’ Proceedings of Asynchronous Design Workshop — Banff Alberta, Birtwistle, G., Davis, A. editors, Springer-Verlag
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1997 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Bardsley, A., Edwards, D. (1997). Compiling the language Balsa to delay insensitive hardware. In: Kloos, C.D., Cerny, E. (eds) Hardware Description Languages and their Applications. IFIP — The International Federation for Information Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35064-6_11
Download citation
DOI: https://doi.org/10.1007/978-0-387-35064-6_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-5387-5
Online ISBN: 978-0-387-35064-6
eBook Packages: Springer Book Archive