Abstract
High-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many IOs. This problem becomes more frequent with FPGAs which have small size limits and even smaller IO pin limits. An IO bottleneck often prevents the maximum FPGA package size from being reached. In this paper, two new FPGA cone partitioning algorithms are presented that have been implemented in the ASYL+ tool set. High-level synthesis is linked to cone partitioning by creating circuit hierarchy from a VHDL description.
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© 1995 IFIP International Federation for Information Processing
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Saucier, G., Brasen, D., Hiol, J.P. (1995). Circuit Partitioning For FPGAs. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_9
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DOI: https://doi.org/10.1007/978-0-387-34920-6_9
Publisher Name: Springer, Boston, MA
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