Abstract
High-level synthesis is a very active research area in VLSI design automation upon which a lot of effort has been spent during the past. However, the high-level synthesis methodology has not yet received the same level of acceptance in industry as logic and RT synthesis. The purpose of this paper is not to give a tutorial1, but rather to discuss some reasons for this lack of acceptance with respect to commercial issues, to analyze what requirements a high-level synthesis tool needs to fulfill to enable a similar boost in a designer’s productivity as logic and RT synthesis tools have and finally to give an outlook on emerging challenges for high-level synthesis tools in the future.
This paper is a revised version of a paper from the IFIP Workshop on Logic and Architecture Synthesis 1993, Grenoble, France.
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Keywords
- Implementation Model
- Very Large Scale Integration
- Design Space Exploration
- Synthesis Tool
- Level Synthesis
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Wehn, N. (1995). High-Level Synthesis: A Critical Assessment. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_29
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DOI: https://doi.org/10.1007/978-0-387-34920-6_29
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