Abstract
This chapter describes the design of a single-cycle 64-bit integer executionALU fabricated in 90 nm dual-Vt CMOS technology, operating at 4 GHz in the 64-bit mode with a 32-bit mode latency of 7 GHz (measured at 1.3V, 25° C). The lower- and upper-order 32-bit domains operate on separate off-chip supply voltages, enabling conditional turn-on/off of the 64-bit ALU mode operation and efficient power-performance optimization. High-speed single-rail dynamic circuit techniques and a sparse-tree semi-dynamic adder core enable a dense layout occupying 280 × 260µm2 while simultaneously achieving (i) low carry-merge fan-outs and inter-stage wiring complexity, (ii) low active leakage and dynamic power consumption, (iii) highDCnoise robustness with maximum low-Vt usage, (iv) single-rail dynamic-compatible ALU write-back bus, (v) simple 2ф 50% duty-cycle timing plan with seamless time-borrowing across phases, (vi) scalable 64-bitALU performance up to 7 GHz measured at 2.1V, 25° C, and (vii) scalable 32-bit ALU performance up to 9 GHz measured at 1.68V, 25° C.
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Mathew, S.K., Anders, M.A., Krishnamurthy, R.K. (2006). High-Performance Energy-Efficient Dual-Supply ALU Design. In: Oklobdzija, V.G., Krishnamurthy, R.K. (eds) High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34047-0_7
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DOI: https://doi.org/10.1007/978-0-387-34047-0_7
Publisher Name: Springer, Boston, MA
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