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Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

Abstract

Processor energy efficiency is a major issue in a majority of products; however, it is difficult to achieve it, as it is in contradiction with the main characteristic of processors, i.e. flexibility provided by embedded software. A given function implemented in random logic could consume 100–1000 times less energy than the same function implemented in a processor and corresponding embedded software. However, flexibility is more and more required, and ultra-low-power processors are mandatory. Only a few techniques have been widely used for the power consumption reduction of microcontrollers and DSP processors. This chapter will review these techniques, which are basically CPI (clocks per instruction) reduction, gated-clock mechanisms, optimal pipeline length, hardware accelerators, reconfigurable units and techniques to reduce leakage power. Several examples will be described in more details, such as some RISC 8-bit and 32-bit microcontrollers as well as some DSP cores. The latter are a good example of the necessary tradeoffs between flexibility and energy efficiency, as many random logic-based accelerators are very often used.

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References

  1. Rabay, J.M. “Managing power dissipation in the generation-after-next wireless systems”, FTFC’99, June 1999, Paris.

    Google Scholar 

  2. Piguet, C. “Parallelism and low-power”, Invited talk, SympA’99, Symposium Architectures de Machines, Rennes, France, 8 June 1999.

    Google Scholar 

  3. Jerraya, A. “Hardware/software codesign”, Summer Course, Orebro, Sweden, 14–16 August, 2000.

    Google Scholar 

  4. Anis, M.; Elmasry, M. Multi-threshold CMOS digital circuits, Kluwer Academic Publishers, 2003.

    Google Scholar 

  5. Vittoz, E. “Weak inversion for ultimate low-power logic”, in Low Power Electronics Design, edited by C. Piguet. CRC Press, 2004, chapter 16.

    Google Scholar 

  6. Heer, C. et al. “Designing low-power circuits: an industrial point of view”, PATMOS 2001, Yverdon, 26–28 September 2001.

    Google Scholar 

  7. Piguet, C.; Schuster, C.; Nagel, J-L. “Optimizing architecture activity and logic depth for static and dynamic power reduction”, Proc. 2nd Northeast Workshop on Circuits and Systems, NewCAS’04, 20–23 June 2004, Montréal, Canada.

    Google Scholar 

  8. Brodersen, R.W. et al. “Methods for true power minimization”, Proc. Int. Conf. on Computer Aided Design. San Jose, California, November 2000, 35–42.

    Google Scholar 

  9. Nose, K.; Sakurai, T. “Optimization of Vdd and Vth for low-power and high-speed applications”, ASPDAC, January 2000, 469–474.

    Google Scholar 

  10. Schuster, C.; Nagel, J-L.; Piguet, C.; Farine, P-A. “Leakage reduction at the architectural level and its application to 16 bit multiplier architectures”, Patmos’04, Santorini Island, Greece, 15–17 September 2004.

    Google Scholar 

  11. Schuster, C.; Piguet, C.; Nagel, J-L.; Farine, P-A. “An architecture design methodology for minimal total power consumption at fixed Vdd and Vth”, J. Low-Power Electronics, 2005, 1, 1–8.

    Article  Google Scholar 

  12. Piguet, C. et al. “Low-power design of 8-bit embedded CoolRISC microcontroller cores”, IEEE JSSC, 1997, 32(7), 1067–1078.

    Google Scholar 

  13. Masgonty, J-M. et al. “Low-power design of an embedded microprocessor”, ESSCIRC’ 96, 16–21 September 1996, Neuchâ tel, Switzerland.

    Google Scholar 

  14. Oh, J.; Pedram, M. “Gated clock routing for low-power microprocessor design”, IEEE Trans. Computer Aided Design of ICs and Systems, 2001, 20(6), 715–722.

    Article  Google Scholar 

  15. PowerChecker, www.bulldast.com.

    Google Scholar 

  16. Keating, M.; Bricaud, P. Reuse methodology manual, Kluwer Academic Publishers, 1999.

    Google Scholar 

  17. Arm, C.; Masgonty, J-M.; Piguet, C. “Double-latch clocking scheme for low-power I.P. cores”, PATMOS 2000, Goettingen, Germany, 13–15 September 2000.

    Google Scholar 

  18. Mosch, Ph. et al. “A72µW, 50 MOPS, 1V DSPfor a hearing aid chip set”, ISSCC’00, San Francisco, 7–9 February, 2000, Session 14, paper 5, 238–239, 2000.

    Google Scholar 

  19. Schlett, M. “Trends in embedded microprocessor design”, IEEE Computer, August 1998, 44–49.

    Google Scholar 

  20. Kuga, M. et al. “DSNS (dynamically-hazard-resolved, statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture”, Computer Architecture, 1991, 4, 14–29.

    Article  Google Scholar 

  21. Michaud, P. “La prédiction de branchement”, SympA’99, Symposium Architectures de Machines, Rennes, France, 8 June 1999.

    Google Scholar 

  22. Omondi, A.R. The microarchitecture of pipelined and superscalar computers. Kluwer Academic Publishers, 1999.

    Google Scholar 

  23. Clark, L.T. et al. “A scalable performance 32b microprocessor”, Proc. ISSCC’2001, San Francisco, 6 February 2001, 230–231.

    Google Scholar 

  24. Rowen, C. et al. “A pipelined 32b NMOS microprocessor”, Proc. ISSCC’84, 1984.

    Google Scholar 

  25. Halfhill, T.R. “ARC 700 Secrets Revealed”, Microprocessor Rep., 21 June 2004, 1–6.

    Google Scholar 

  26. Tran, C. et al. “The MIPS32 24KE core family”, Microprocessor Rep., 31 May 2005, 1–9.

    Google Scholar 

  27. Krewell, K. “Multicore showdown”, Microprocessor Rep., 31 May 2005, 1–5.

    Google Scholar 

  28. Perotto, J-F; Lamothe, C.; Arm, C. et al. “An 8-bit multitask micropower RISC core”, JSSC, 1994, 29(18), 986–991.

    Google Scholar 

  29. “Sun’s Big Splash”, IEEE Spectrum, January 2005, 50–54.

    Google Scholar 

  30. Frantz, G. “Digital signal processor trends”, IEEE Micro, November-December 2000, 52–59.

    Google Scholar 

  31. http://www.ceva-dsp.com/

    Google Scholar 

  32. Halfill, T.R. “MIPS24KE: better late than never”, Microprocessor Rep., 31 May 2005.

    Google Scholar 

  33. Halfhill, T.R. “ARC’s preconfigured cores”, Microprocessor Rep., 14 March 2005, 1–6.

    Google Scholar 

  34. Halfhill, T.R. “Tensilica tackles bottlenecks”, Microprocessor Rep., 31 May 2004.

    Google Scholar 

  35. Verbauwhede, I.; Nicol, Ch. “Low power DSP’s for wireless communications”, Proc. ISLPED’00, 2000, Rapallo, Italy, 303310.

    Google Scholar 

  36. Cravotta, R. “Targeted DSPs take aim” EDN, 28 April 2005 www.edn.com.

    Google Scholar 

  37. David, R. et al., “Low-power reconfigurable processors”, in Low power electronics design, ed. C. Piguet. CRC Press, 2004, Chapter 20.

    Google Scholar 

  38. Rampogna, F. et al., “MACGIC, a low-power, re-configurable DSP”, in Low power electronics design, ed. C. Piguet. CRC Press, 2004.

    Google Scholar 

  39. Rabaey, J.M. “Reconfigurable processing: the solution to low-power programmable DSP”, Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), April 1997.

    Google Scholar 

  40. Verbauwhede, I.; Piguet, C.; Schaumont, P.; Kienhuis, B. “Architectures and design techniques for energy-efficient embedded DSP and multimedia processing”, Embedded Tutorial, Proc. DATE’04, Paris, 16–20 February 2004, Paper 7G, 988–995.

    Google Scholar 

  41. Baron, M. “2004: top features, low power”, Microprocessor Rep., 18 January 2004.

    Google Scholar 

  42. Cravotta, R. “2004 DSP directory”, EDN, 29 April 2004, 49–67.

    Google Scholar 

  43. Halfhill, T.R. “PicoChip makes a big MAC”, Microprocessor Rep., 14 October 2003.

    Google Scholar 

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Piguet, C. (2006). Ultra-Low-Power Processor Design. In: Oklobdzija, V.G., Krishnamurthy, R.K. (eds) High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34047-0_1

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  • DOI: https://doi.org/10.1007/978-0-387-34047-0_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-28594-8

  • Online ISBN: 978-0-387-34047-0

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