Abstract
Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.
This paper reports of a new Parallel Multi-Level VLSI Simulator (PMLS) for general purpose parallel machines which combines multi-leveling and exploitation of parallelism at the circuit level.
The VLSI simulator is implemented in the object-oriented language POOL and runs on the DOOM machine.
The paper surveys briefly the principles of digital circuit simulation, as well as the possibilities of exploiting parallelism, and describes the design and implementation of the simulator. Preliminary performance figures are also given.
Research partially funded by ESPRIT Project 415: Parallel Architectures and Languages for Advanced Information Processing — A VLSI-Directed Approach.
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Aposporidis, E., Lohnert, F. (1989). Multi-level simulator for VLSI on the parallel object-oriented machine. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 365. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540512845_51
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DOI: https://doi.org/10.1007/3540512845_51
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