Skip to main content

Multi-level simulator for VLSI on the parallel object-oriented machine

  • Project 415 Presentations
  • Conference paper
  • First Online:
  • 136 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 365))

Abstract

Simulation is a key element in modern and future digital circuit design. However, simulation becomes a bottleneck with increasing design complexity. There are mainly two ways to get out of this situation: reduction of the simulation load through multi-level simulation and acceleration of the simulation through exploitation of parallelism.

This paper reports of a new Parallel Multi-Level VLSI Simulator (PMLS) for general purpose parallel machines which combines multi-leveling and exploitation of parallelism at the circuit level.

The VLSI simulator is implemented in the object-oriented language POOL and runs on the DOOM machine.

The paper surveys briefly the principles of digital circuit simulation, as well as the possibilities of exploiting parallelism, and describes the design and implementation of the simulator. Preliminary performance figures are also given.

Research partially funded by ESPRIT Project 415: Parallel Architectures and Languages for Advanced Information Processing — A VLSI-Directed Approach.

This is a preview of subscription content, log in via an institution.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Mehring,P., Aposporidis,E.:Multi-level Simulator for VLSI—an overview;Proc. PARLE—Parallel Architectures and Languages Europe, Eindhoven, June 15–19, 1987; Vol. 1, pp. 446–460

    Google Scholar 

  2. Aposporidis,E., Lohnert,F.:Multi-Level Simulator for VLSI — Design and Implementation in POOL; Workshop ”ESPRIT Project 415—Parallel Architectures and Languages for Advanced Information Processing—A VLSI-Directed Approach”, 5th Annual ESPRIT Conference, Brussels, Nov. 14–18, 1988.

    Google Scholar 

  3. Bronnenberg,W., Nijman,L., Odijk,E., Twist,R.: DOOM: A Decentralized Object-Oriented Machine; IEEE Micro, October 1987, pp. 52–69

    Google Scholar 

  4. Bronnenberg,W.: POOL and DOOM, a survey of ESPRIT 415, Subproject A, Philips Research Labs.; this Conference

    Google Scholar 

  5. Albert, I., Mueller-Schloer, C., Schwaertzel, H:CAD-Systeme fuer die industrielle Rechnerentwicklung; Informatik-Spektrum (1986)9, pp. 14–28

    Google Scholar 

  6. Rammig,F.,J.: Mixed Level Modelling and Simulation of VLSI Systems; Logic Design and Simulation, North Holland, 1986, pp. 95–134

    Google Scholar 

  7. Ghosh,J.: Dynamic Multi-Level Simulation of Digital Hardware Designs; Simulation, 1987, pp. 247–252

    Google Scholar 

  8. Blunden, D.F., Boyce, A.H., Taylor, G.:Logic Simulation—Part 1; The Marconi Review, Vol. XL, No. 206, Third Quarter 1977, pp. 157–171

    Google Scholar 

  9. Aposporidis,E., Jud,W.: Logik— und Fehlersimulation kunden-spezifischer Schaltungen; 10. Intern. Kongress Mikro-Elektronik, Muenchen, 9.–11. Nov. 1982, pp. 414–423

    Google Scholar 

  10. Misra,J.: Distributed Discrete-Event Simulation, Computing Surveys, March 1986, pp. 39–65

    Google Scholar 

  11. Jefferson,D., Sowizral,H.: Fast concurrent simulation using the time warp mechanism; SCS Multiconference, San Diego, Jan. 85, Part: Distributed Simulation, pp. 63–69

    Google Scholar 

  12. Jefferson,D.: Virtual Time; ACM Transactions on Programming Languages and Systems, July 1985, pp. 404–424

    Google Scholar 

  13. Abramovici, M., Levendel, Y.H. Menon, P.R.: A Logic Simulation Machine; IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2 (1983), pp. 82–94

    Article  Google Scholar 

  14. Samadi,B.: Distributed Simulation: Performance and Analysis; PhD Thesis, UCLA, 1985

    Google Scholar 

  15. Berry,O.: A Testbed for the Time Warp Distributed Simulation Mechanism; Trans. of the Society for Comp. Simulation, 1986, pp. 135–157

    Google Scholar 

  16. Hoppe,F.: Accelerated Logic Simulation using Parallel Processing; COMPEURO '88, Brussels, pp. 156–163

    Google Scholar 

  17. Hwang,S.Y., Blank,T., Choi,K.: ”Incremental Functional Simulation of Digital Circuits”, Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1987, pp 392–395

    Google Scholar 

  18. Greer,D.L.: The Quick Simulator Benchmark; VLSI Systems Design, Nov. 1987, pp. 40–57

    Google Scholar 

  19. Schaefer,P.,Schnoebelen, Ph.: Specification of a pipelined event driven simulator using FP2; Proc. PARLE-Parallel Architectures and Languages Europe, Eindhoven, June 15–19, 1987, pp. 311–328

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Eddy Odijk Martin Rem Jean-Claude Syre

Rights and permissions

Reprints and permissions

Copyright information

© 1989 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Aposporidis, E., Lohnert, F. (1989). Multi-level simulator for VLSI on the parallel object-oriented machine. In: Odijk, E., Rem, M., Syre, JC. (eds) PARLE '89 Parallel Architectures and Languages Europe. PARLE 1989. Lecture Notes in Computer Science, vol 365. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540512845_51

Download citation

  • DOI: https://doi.org/10.1007/3540512845_51

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-51284-4

  • Online ISBN: 978-3-540-46183-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics