An Application of Genetic Algorithms to Floorplanning of VLSI

Abstract

Floorplanning of VLSI design is one of the key design flows which decides chip size, electrical characteristics, timing constrains, etc., of final silicon chip. Many useful floorplan tools are available in the industry. Those tools provide very user-friendly interactive environment and also provide useful information to proceed with chip design. However, construction and decision-making of floorplan design itself relies on the insight of human being. Therefore, the result varies depending on “who did it” and what initial condition was given at first. In this paper, authors propose an application of Genetic Algorithms to floorplanning for the purpose of providing better initial conditions as a starting point of design work to novice designers. A floorplan placement model suitable to Genetic Algorithm is discussed. Computational experiment is also carried out and results suggests practical possibility.