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Measuring the vulnerability of interconnection networks in embedded systems

  • V. Lakamraju
  • Z. Koren
  • I. Koren
  • C. M. Krishna
Workshop on Embedded HPC Systems and Applications Devesh Bhatt, Honeywell Technology Center, USA Viktor Prasanna, Univ. of Southern California, USA
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

Studies of the fault-tolerance of graphs have tended to largely concentrate on classical graph connectivity. This measure is very basic, and conveys very little information for designers to use in selecting a suitable topology for the interconnection network in embedded systems. In this paper, we study the vulnerability of interconnection networks to the failure of individual links, using a set of four measures which, taken together, provide a much fuller characterization of the network. Moreover, while traditional studies typically limit themselves to uncorrelated link failures, our model deals with both uncorrelated and correlated failure modes. This is of practical significance, since quite often, failures in networks are correlated due to physical considerations.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • V. Lakamraju
    • 1
  • Z. Koren
    • 1
  • I. Koren
    • 1
  • C. M. Krishna
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of MassachusettsAmherst

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