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PACE: Processor architectures for circuit emulation

  • Reiner Kolla
  • Oliver Springauf
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circuit sizes and clock frequencies. In order to evaluate the performance of such programmable designs, we also need software methods for code generation from circuit descriptions. We propose a combination of scheduling and routing algorithms for embedding calculations into the target architecture.

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References

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    A. DeHon, Reconfigurable Architectures for General-Purpose Computing, A.I. Report #1586, Massachusetts Institute of Technology, October 1996Google Scholar
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    F Gasperoni, U. Schwiegelshohn, J. Turek, Cyclic Scheduling on p Processors: Optimality and Periodicity, Report #0396, Faculty of Electrical Engineering, Universität Dortmund.Google Scholar
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    D. Jones, D. M. Lewis, A Time Multiplexed FPGA Architecture for Logic Emulation, Proc. Third ACM International Symposion on FPGAs, ACM, 1995Google Scholar
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    G. C. Sih, E. A. Lee, A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures, IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 2, February 1993Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Reiner Kolla
    • 1
  • Oliver Springauf
    • 1
  1. 1.Lehrstuhl für Technische InformatikUniversität WürzburgGermany

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