PACE: Processor architectures for circuit emulation

  • Reiner Kolla
  • Oliver Springauf
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)


We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circuit sizes and clock frequencies. In order to evaluate the performance of such programmable designs, we also need software methods for code generation from circuit descriptions. We propose a combination of scheduling and routing algorithms for embedding calculations into the target architecture.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Reiner Kolla
    • 1
  • Oliver Springauf
    • 1
  1. 1.Lehrstuhl für Technische InformatikUniversität WürzburgGermany

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