Hardware reconfigurable neural networks

  • Jean-Luc Beuchat
  • Jacques-Olivier Haenni
  • Eduardo Sanchez
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)


This paper presents the concept of reconfigurable systems using the example of a digital hardware implementation of neural networks, as well as RENCO, a platform very well-suited for the prototyping of such systems. RENCO is a network computer containing a reconfigurable part composed of four Flex10K FPGAs from Altera (10K130 or 1OK250).


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  1. 1.
    Z. Salcic, A. Smailagic. Digital System Design and Prototyping Using Field Programmable Logic. Kluwer Academic Publishers, Boston, 1997.Google Scholar
  2. 2.
    E. Sanchez. Field Programmable Gate Array (FPGA) Circuits. In E. Sanchez, M. Tomassini (eds.). Towards Evolvable Hardware. Springer-Verlag, Berlin, 1997, pp. 1–18.Google Scholar
  3. 3.
    J. Villasenor, W. H. Mangione-Smith. Configurable Computing. Scientific American, June 1997, pp. 54–59.Google Scholar
  4. 4.
    M. Slater. The Many Faces of Network Computers. Microprocessor Report, Vol. 10, num. 16, 1996, p. 3.Google Scholar
  5. 5.
    Motorola. MC68360, Quad Integrated Communications Controller, User's Manual. 1993.Google Scholar
  6. 6.
    Altera Corporation. EPF10K130, Embedded Programmable Logic Device. San Jose, April 1997.Google Scholar
  7. 7.
    RTEMS Home Page, http://Lancelot.gcs.redstone.army.mil/rterns.html.Google Scholar
  8. 8.
    Kaffe, A free virtual machine to run Java(tm) code, http://www.kaffe.org/.Google Scholar
  9. 9.
    M. A. Lehr, B. Widrow. 30 Years of Adaptative Neural Networks: Perceptron, Madaline and Backpropagation. Proc. IEEE, 78(9): 1425–1442, September 1990.Google Scholar
  10. 10.
    S. Sakaue, T. Kohda, H. Yamamoto, S. Maruno, Y. Shimeki. Reduction of Required Bits for Backpropagation Applied to Pattern Recognition. IEEE Transactions on Neural Networks, Vol. 4, no. 2, March 1993, pp. 270–275.CrossRefGoogle Scholar
  11. 11.
    J.G. Eldredge and B.L. Hutchings. Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAS for Custom Comput ing Machines, pages 180–188, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Jean-Luc Beuchat
    • 1
  • Jacques-Olivier Haenni
    • 1
  • Eduardo Sanchez
    • 1
  1. 1.Logic Systems LaboratorySwiss Federal Institute of TechnologyLausanne

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