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On reconfgurable co-processing units

  • Reiner W. Hartenstein
  • Michael Herz
  • Thomas Hoffmann
  • Ulrich Nageldinger
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

In the last years reconfigurable computing grew from a niche application to an important R&D scene. But also today most architectures lack essential features for the convenient use as a co-processing unit. E.g. embedded accelerator design with traditional FPGAs is very similar to sophisticated ASIC-design due to the bit-level granularity of FPGAs. In this paper important topics for reconfigurable platforms in multitasking systems are discussed. Run-time programmability as well as rapid application implementation using high-level languages are illustrated. Besides the underlying concepts the hardware implementation of a field-programmable ALU array (FPAA), the KrAA-III, is explained.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Reiner W. Hartenstein
  • Michael Herz
    • 1
  • Thomas Hoffmann
    • 1
  • Ulrich Nageldinger
    • 1
  1. 1.University of KaiserslauternKaiserslauternGermany

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