Evaluation of a low-power reconfigurable DSP architecture

  • Arthur Abnous
  • Katsunori Seno
  • Yuji Ichikawa
  • Marlene Wan
  • Jan Rabaey
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)


Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Arthur Abnous
    • 1
  • Katsunori Seno
    • 2
  • Yuji Ichikawa
    • 3
  • Marlene Wan
    • 1
  • Jan Rabaey
    • 1
  1. 1.Dept. of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeley
  2. 2.Sony CorporationJapan
  3. 3.SHARP CorporationJapan

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