Synthesizing reconfigurable sequential machines using Tabular models

  • Kamlesh Rath
  • Jian Li
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)


Two common problems we face in implementing reconfigurable systems on currently available FPGA chips are: (1) fitting designs which are too big for available hardware resources on a single FPGA chip, (2) lack of synthesis tools for high-level specifications. One solution to address the first problem is partial reconfiguration or run-time reconfiguration which requires only loading a portion of the design onto a FPGA chip at one time. In this paper, we present a synthesis methodology which starts from high-level system specifications and synthesizes run-time reconfigurable systems. Our approach uses tabular models as intermediate data structures. Tabular representations provide a convenient platform for separating control and data-path, and dividing the data-path into separate control-paths. This makes our approach very useful in synthesis targeted at implementations that depend on run-time reconfiguration to fit bigger designs on currently available FPGA chips.


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  1. 1.
    J. R. Hauser and J. Wawrzynek, “Garp: A mips processor with a reconfigurable coprocessor,” in IEEE Workshop on FPGAs for Custom Computing Machines, pp. 24–33, 1997.Google Scholar
  2. 2.
    J. Hadley and B. Hutchings, “Design methodologies for partially reconfigured systems,” in IEEE Workshop on FPGAs for Custom Computing Machines, pp. 78–84, 1995.Google Scholar
  3. 3.
    E. Lemoine and D. Merceron, “Run-time reconfiguration of fpga for scanning genomic databases,” in IEEE Workshop on FPGAs for Custom Computing Machines, pp. 90–98, 1995.Google Scholar
  4. 4.
    J. Li and R. K. Gupta, “HDL Optimization Using Timed Decision Tables,” in Proceedings of the 33 rd Design Automation Conference, pp. 51–54, June 1996.Google Scholar
  5. 5.
    J. Li and R. K. Gupta, “Limited exception modeling and its use in presynthesis optimizations,” in Proceedings of the 34 th Design Automation Conference, June 1997.Google Scholar
  6. 6.
    K. Rath, M. E. Tuna, and S. D. Johnson, “Behavior tables: A basis for system representation and transformational system synthesis,” in Proceedings of the International Conference on Computer Aided Design (ICCAD), IEEE, Nov. 1993.Google Scholar
  7. 7.
    G. D. Micheli, D. C. Ku, F. Mailhot, and T. Truong, “The Olympus Synthesis System for Digital Design,” IEEE Design and Test Magazine, pp. 37–53, Oct. 1990.Google Scholar
  8. 8.
    D. Ku, Hardware C — A Language for Hardware Design Version 2.0.Google Scholar
  9. 9.
    J. Li and R. K. Gupta, “Timed Decision Table: A Model for System Representation and Optimization,” Technical Report UIUCDCS-R-96-1971, University of Illinois, 1996.Google Scholar
  10. 10.
    J. Li and R. K. Gupta, “Decomposition of Timed Decision Tables and its Use in Presynthesis Optimizations,” in Proceedings of the IEEE International Conference on Computer-Aided Design, November 1997.Google Scholar
  11. 11.
    P. K. Chan and S. Mourad, Digital Design Using Field Programmable Gate Arrays. Prentice Hall, 1994.Google Scholar
  12. 12.
    J. Li and R. K. Gupta, “System modeling and presynthesis using timed decision tables,” TVLSI, 1997. (submitted).Google Scholar
  13. 13.
    S. D. Johnson, Synthesis of Digital Designs from Recursion Equations. Cambridge: MIT Press, 1984. ACM Distinguished Dissertation 1984.Google Scholar
  14. 14.
    Xilinx, XC6200 Data Sheet, 1996.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Kamlesh Rath
    • 1
  • Jian Li
    • 2
  1. 1.University of Texas at DallasRichardson
  2. 2.University of Illinois Urbana-ChampaignIllinois

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