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Synthesizing reconfigurable sequential machines using Tabular models

  • Kamlesh Rath
  • Jian Li
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

Two common problems we face in implementing reconfigurable systems on currently available FPGA chips are: (1) fitting designs which are too big for available hardware resources on a single FPGA chip, (2) lack of synthesis tools for high-level specifications. One solution to address the first problem is partial reconfiguration or run-time reconfiguration which requires only loading a portion of the design onto a FPGA chip at one time. In this paper, we present a synthesis methodology which starts from high-level system specifications and synthesizes run-time reconfigurable systems. Our approach uses tabular models as intermediate data structures. Tabular representations provide a convenient platform for separating control and data-path, and dividing the data-path into separate control-paths. This makes our approach very useful in synthesis targeted at implementations that depend on run-time reconfiguration to fit bigger designs on currently available FPGA chips.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Kamlesh Rath
    • 1
  • Jian Li
    • 2
  1. 1.University of Texas at DallasRichardson
  2. 2.University of Illinois Urbana-ChampaignIllinois

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