Advertisement

Temporal partitioning for partially-reconfigurable-field-programmable gate

  • John Spillane
  • Henry Owen
Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslauteren, Germany
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1388)

Abstract

The recent introduction of partially-reconfigurable field-programmable gate arrays (PRFPGAs) has led to the need for new algorithms suited for use with these devices. Although algorithms developed for use with field-programmable gate arrays can be applied to PRFPGAs, these algorithms do not take advantage of features available in these new devices.

This paper examines the applicability of PRFPGAs in hardware emulation systems. A partitioning algorithm known as temporal partitioning is introduced for use with PRFPGA-based hardware emulation systems.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    D. Brasen, J.P. Hiol, G. Saucier, “Finding Best Cones From Random Clusters For FPGA Package Partitioning,” IFIP International Conference on Very Large Scale Integration, Aug 1995, pp. 799–804.Google Scholar
  2. [2]
    Gateley, et. al., “UltraSPARCtm-I Emulation,” 32nd ACM/IEEE Design Automation Conference, Jun 1995, pp. 13–18.Google Scholar
  3. [3]
    S. Smith, M. Mercer, B. Brock, “Demand Driven Simulation: BACKSIM,” 24th ACM/IEEE Design Automation Conference, Jun 1987, pp. 181–187. *** DIRECT SUPPORT *** A0008D07 00003Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • John Spillane
    • 1
  • Henry Owen
    • 2
  1. 1.Department of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlanta
  2. 2.Department of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlanta

Personalised recommendations