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Parallel implementation of fractal image compression using multiple digital signal processors

  • S. K. Chow
  • M. Gillies
  • S. L. Chan
Poster Session II
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1351)

Abstract

Fractal image compression technique provides very high compression ratios for natural scenes and has the advantage of being resolution independent. However, the encoding process based on the self-similarity search between range and domain blocks is very computationally intensive. This prohibits their real-time application. In this paper, we first propose two parallel schemes and then present one of the parallel implementations on multiple DSP cards. This card is developed for use as a low-cost, general-purpose digital signal-processing card for ISA bus systems. The experimental results show that the proposed parallel implementation yields a significant speedup compared with serial computation. This implementation provides a cost-effective solution for speeding up the fractal image compression and makes it competitive with other methods.

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References

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • S. K. Chow
    • 1
  • M. Gillies
    • 1
  • S. L. Chan
    • 1
  1. 1.School of Engineering and TechnologyDeakin UniversityAustralia

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