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Wavelet transform architectures: A system level review

  • M. Ferretti
  • D. Rizzo
Poster Session C: Compression, Hardware & Software, Image Databases, Neural Networks, Object Recognition & Construction
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1311)

Abstract

In this paper we review the architectures designed for wavelet transforms, with the purpose to highlight their suitability for inclusion in codee systems. Indeed, common VLSI cost functions (such as AT2) are insufficient to evaluate architectures for compression. At the system level, quantization and coding have processing requirements that must be taken into account when designing the transform engine. The hierarchical structure of wavelet transform allows to use "pyramid" algorithms that optimize latency and processor utilization; on-line solutions try to minimize buffering memory. Such approaches can be substituted with more standard ones, if data reordering is mandatory to apply a good quantization strategy. An upcoming commercial solution offers a sound comparison paradigm.

Keywords

Discrete Wavelet Transform Clock Cycle VLSI Architecture Parallel Filter Pyramid Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • M. Ferretti
    • 1
  • D. Rizzo
    • 1
  1. 1.Dip. Informatica e SistemisticaUniv. of PaviaItaly

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