Auto-configurable array for GCD computation
A novel one-directional pass-through array for the computation of integer greatest common divisor is designed and implemented on Atmel FPGA. The design is based on the plus-minus GCD algorithm and works in LSB pipelined manner. In contrast with previous designs, the length of the new array is independent of the length of the operands: arbitrary long integers can be processed in multiple passes. The array is auto-configurable: at each step, one new cell is configured according to the input from the previous computation. Preliminary experiments show that for 100 bits a speed-up of 4 over software can be obtained using one 6010 Atmel chip.
Unable to display preview. Download preview PDF.
- 1.R. P. Brent and H. T. Kung. A systolic algorithm for integer GCD computation. In K. Hwang, editor, Procs. of the 7th Symp. on Computer Arithmetic, pages 118–125. IEEE Computer Society, June 1985.Google Scholar
- 2.P. Dewilde and E. Deprettere. Architectural synthesis of large, nearly regular algorithms. Ann. Telecom., 46(1-2):49–59, 1991.Google Scholar
- 3.T. Jebelean. Comparing several GCD algorithms. In E. Swartzlander, M. J. Irwin, and G. Jullien, editors, ARITH-11: IEEE Symposium on Computer Arithmetic, pages 180–185, Windsor, Canada, June 1993.Google Scholar
- 4.T. Jebelean. Design of a systolic coprocessor for rational addition. In P. Capello, C. Mongenet, G-R. Perrin, P. Quinton, and Y. Robert, editors, ASAP '95, Strasbourg, France, Judy 1995, pages 282–289. IEEE Computer Society Press, 1995.Google Scholar