Virtual radix array processors (V-RaAP)
The V-RaAP software (written in C++) enables the implementation of Radix Array Processors, expressed as iterative equations, into Field Programmable Gate Arrays (FPGA's). The V-RaAP software is not a compiler which translates C++ into VHDL. Rather, the V-RaAP C++ program is a high-level explicit description of structural VHDL that implements a RaAP algorithm in a hierarchical manner. When the C++ program is executed it automatically generates a number of VHDL files containing the entity and architecture specifications of the components which make up the final design. The code generated is equivalent to a hand crafted VHDL design. This is made possible because the RaAP iterative algorithm contains all the information specifying the functionality and interconnects of the architectures.
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- 1.Ibrahim, M K, (1993) Radix Multiplier Structures: A structured design methodology. IEE Proceedings part E, 140, pp 185–190.Google Scholar
- 2.Aggoun, A, Ibrahim, M K, and Ashur, A, (1995) Radix Multiplication Algorithms, International Journal of Electronics, Vol.79, No.3, pp329–345.Google Scholar
- 3.Bashagha, A E, Ibrahim, M K, (1995) A new high radix non-restoring divider architecture, International Journal of Electronics, Vol.79. No4, pp.455–470.Google Scholar
- 4.Ashur, A, Ibrahim, M K, and Aggoun, A., (1996) Systolic digit serial multiplier, IEE Proceedings-Circuits, Devices and Systems, Vol. 143, No. 1, pp 14–20Google Scholar
- 5.Bashagha, A E, Ibrahim, M K, (1996) Non-restoring radix 2k square rooting algorithm, the Journal of Circuits and Systems, and Computers, 1996, Vol.6, No.3, pp 267–285.Google Scholar
- 6.Bashagha, A E, Ibrahim, M K (1996), High radix digit-serial division, IEE Proceedings on Circuits, Systems, and Devices, Vol 143Google Scholar
- 7.Aggoun, A, Ibrahim, M K, and Ashur, A, Bit-level pipelined digit serial Processors, Accepted for publications in the IEEE Transactions on Circuits and Systems.Google Scholar
- 8.Mekhallalati, M, Ibrahim, M K, Ashur, A, Radix Iterative Parallel Modular Multiplier, Accepted for publication in the Journal of Circuits and Systems, and Computers.Google Scholar
- 9.Mekhallalati, M, Ibrahim, M K, Ashur, A, Novel Radix Finite Field Multiplier for GF(2N), Accepted for publication in the Journal of VLSI Signal Processing.Google Scholar
- 10.Gschwind, M and Salapura, V., A VHDL design methodology for FPGAs, Field Programmable Logic and Applications, 5th International workshop, FPL95, Oxford, UK, pp209-226.Google Scholar