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Virtual radix array processors (V-RaAP)

  • B. Bramer
  • D. Chauhan
  • M. K. Ibrahim
  • A. Aggoun
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)

Abstract

The V-RaAP software (written in C++) enables the implementation of Radix Array Processors, expressed as iterative equations, into Field Programmable Gate Arrays (FPGA's). The V-RaAP software is not a compiler which translates C++ into VHDL. Rather, the V-RaAP C++ program is a high-level explicit description of structural VHDL that implements a RaAP algorithm in a hierarchical manner. When the C++ program is executed it automatically generates a number of VHDL files containing the entity and architecture specifications of the components which make up the final design. The code generated is equivalent to a hand crafted VHDL design. This is made possible because the RaAP iterative algorithm contains all the information specifying the functionality and interconnects of the architectures.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • B. Bramer
    • 1
  • D. Chauhan
    • 1
  • M. K. Ibrahim
    • 1
  • A. Aggoun
    • 1
  1. 1.DSP Systems Research Group Faculty of Computing Sciences and EngineeringDe Montfort UniversityThe GatewayUK

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