A reconfigurable data-localised array for morphological algorithms

  • Anjit Sekhar Chaudhuri
  • Peter Y. K. Cheung
  • Wayne Luk
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)


This paper describes a parallel array architecture for performing morphological operations on images using dynamically reconfigurable Field Programmable Gate Arrays. The key feature of this architecture is the data-localised arrangement, which significantly reduces data flow and continuous reconfiguration, which leads to efficient utilisation of the area. The development of implementations of the various possible operations in morphological algorithms, using skeletonisation as an example, is discussed.


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  1. [1]
    L. Abbott, R. M. Haralick & X. Zhuang, “Pipeline Architectures for Morphologic Image Analysis”, Machine Vision & Applications, pp. 23–40, 1988.Google Scholar
  2. [2]
    P. Y. K. Cheung, “Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research”, this volume.Google Scholar
  3. [3]
    S. Churcher, T. Kean & B. Wilkie, “The 6200 Fastmap Processor Interface”, in Field Programmable Logic & Applications, W. Moore & W. Luk (Eds.), pp. 36–43, LNCS 975, Springer 1995.Google Scholar
  4. [4]
    C. R. Giardina & E.R. Dougherty, “Morphological Methods in Image and Signal Processing”, Prentice Hall, 1988Google Scholar
  5. [5]
    A. C. P. Loui, A. N. Venetsanopoulos & K. C. Smith, “Flexible Architectures for Morphological Image Processing and Analysis”, IEEE Transactions on Circuits & Systems for Video Technology, Vol. 2, No. 1, pp. 72–83, March 1992.Google Scholar
  6. [6]
    W. Luk, N. Shirazi & P. Y. K. Cheung, “Modelling and Optimising Run-Time Reconfigurable Systems”, IEEE Symposium on FPGAs for Custom Computing Machines, 1996.Google Scholar
  7. [7]
    W. Luk, N. Shirazi and P. Y. K. Cheung, “Compilation Tools for Run-Time Reconfigurable Designs”, IEEE Symposium on Field-Programmable Custom Computing Machines, 1997.Google Scholar
  8. [8]
    W. Luk, T. Wu & I. Page, “Hardware-Software Co-design of Multidimensional Programs”, IEEE Workshop on FPGAs for Custom Computing Machines, 1994.Google Scholar
  9. [9]
    H. Park & R. T. Chin, “Optimal Decomposition of Convex Morphological Structuring Elements for 4-Connected Parallel Array Processors”, IEEE Transactions on Pattern Analysis & Machine Intelligence, Vol. 16, No.3, pp. 304–313, March 1994.Google Scholar
  10. [10]
    I. Pitas & A. N. Venetsanopoulos, “Morphological Shape Decomposition”, IEEE Transactions on Pattern Analysis & Machine Intelligence, Vol. 12, No. 1, pp. 38–45, January 1990.Google Scholar
  11. [11]
    S. R. Sternberg, “Computer Architectures Specialized for Mathematical Morphology”, Algorithmically Specialized Parallel Computers, pp. 169–176, 1985.Google Scholar
  12. [12]
    S. Trimberger, D. Carberry, A. Johnson & J. Wong, “A Time-Multiplexed FPGA”, IEEE Symposium on Field-Programmable Custom Computing Machines, 1997.Google Scholar
  13. [13]
    D. Wang & D.-C. He, “A Fast Implementation of 1-D Grayscale Morphological Filters”, IEEE Transactions on Circuits and Systems — 11: Analog & Digital Signal Processing, Vol. 41, No. 9, pp. 634–636, September 1992.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Anjit Sekhar Chaudhuri
    • 1
  • Peter Y. K. Cheung
    • 1
  • Wayne Luk
    • 2
  1. 1.Department of Electrical & Electronic EngineeringImperial College of Science, Technology & MedicineExhibition RoadUK
  2. 2.Department of ComputingImperial College of Science, Technology & Medicine180 Queen's GateUK

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