Fast parallel implementation of DFT using configurable devices
In this paper we propose a fast parallel implementation of Discrete Fourier Transform (DFT) using FPGAs. Our design is based on the Arithmetic Fourier Transform (AFT) using zero-order interpolation. For a given problem of size N, AFT requires only O(N2) additions and O(N) real multiplications with constant factors. Our design employes 2p + 1 PEs (1 ≤ p ≤ N), O(N) memory and fixed 1/O with the host. It is scalable over p (1 ≤ p ≤ N) and can solve larger problems with the same hardware by increasing the memory. All the PEs have fixed architecture. Our implementation is faster than most standard DSP designs for FFT. It also outperforms other FPGA-based implementations for FFT, in terms of speed and adaptability to larger problems.
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