An hardware/software partitioning algorithm for custom computing machines

  • Anton Velinov Chichkov
  • Carlos Beltrán Almeida
Design Tools
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)


In this paper an Hardware/Software partitioning algorithm is presented. Appropriate cost and performance estimation functions were developed, as well, as techniques for their automated calculation. The partitioning algorithm that explores the parallelism in acyclic code regions is part of a larger tool kit specific for custom computing machines. The tool kit includes a parallelising compiler, an hardware/software partitioning program, as well as, a set of programs for performance estimation and system implementation. It speeds up the computationally intensive tasks using a FPGA based processing platform to augment the functionality of the processor with new operations and parallel capacities. An example was used to demonstrate the proposed partitioning techniques.


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  1. [1]
    P. Athanas and H.Silverman, “Processor reconfiguration trough instructionset metamorphosis: architecture and compiler”, Computer, vol. 28, no. 3,pp. 11–18, March 1993.Google Scholar
  2. [2]
    Alfred V. Aho, Ravi Sethi and Jefferey D. Ullman, “Compilers: Principles, Techniques and Tools”, Addison Wesley, 1986.Google Scholar
  3. [3]
    Peter M. Athanas, “An Adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration”, Technical Report LEMS-101, Brown University, February, 1992.Google Scholar
  4. [4]
    Rolf Ernst Jorg Henkel Thomas Benner, “Hardware-Software Co-synthesis for Microcontrollers”, IEEE Design & Test of Computers, December 1993, page 64.Google Scholar
  5. [5]
    Rajesh Kumar Gupta, “Co-Synthesis of Hardware and Software for Digital Embedded Systems”, Ph.D. dissertation Stanford University, December 10, 1993.Google Scholar
  6. [6]
    D. D. Gajski, Frank Vahid Sanjiv Narayan Jie “Specification and design of embedded systems”, Gong University of California at Irvine. PTR Prentice Hall 1994.Google Scholar
  7. [7]
    Anton Chichkov, C. Beltrán Almeida, “Identification and Optimisation of Parallelism in Hardware/Software Partitioning”, International Workshop on Logic and Architecture Synthesis, Grenoble France, December 1996.Google Scholar
  8. [8]
    F. Kurdahi, Ms. Min Xu, “Area & Timing Estimation Techniques for Lookup Table-Based FPGA with Application to High-Level Synthesis”, International Workshop on Logic and Architecture Synthesis, Grenoble France, December 1996.Google Scholar
  9. [9]
    John L. Hennessy, David A. Patterson, “Computer Architecture a Quantitative Approach”, Morgan Kaufmann Publishers, INC. San Mateo, California.Google Scholar
  10. [10]
    Xilinx, “The Programmable Logic Data Book”, 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Anton Velinov Chichkov
    • 1
  • Carlos Beltrán Almeida
    • 1
  1. 1.INESC/ISTLisbonPortugal

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