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Technology mapping of LUT based FPGAs for delay optimisation

  • Xiaochun Lin
  • Erik Dagless
  • Aiguo Lu
Design Tools
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)

Abstract

This paper presents a new LUT based technology mapping approach for delay optimisation. To optimise the circuit delay after layout, the wire delays are taken into account in our delay model. In addition, an effective approach is proposed to trade-off the CLB delays and the wire delays so as to minimise the whole circuit delay. The trade-off is achieved in two phases, mapping for area optimisation followed by new delay reduction techniques. Based on a standard set of benchmark examples, experimental results after PPR layout have shown that the proposed approach outperforms state-of-the-art approaches.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Xiaochun Lin
    • 1
  • Erik Dagless
    • 1
  • Aiguo Lu
    • 2
  1. 1.Dept. of Electrical & Electronic EngineeringUniversity of BristolUK
  2. 2.Institute of Electronic Design AutomationTechnical University of MunichMunichGermany

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