Abstract
This paper presents a new LUT based technology mapping approach for delay optimisation. To optimise the circuit delay after layout, the wire delays are taken into account in our delay model. In addition, an effective approach is proposed to trade-off the CLB delays and the wire delays so as to minimise the whole circuit delay. The trade-off is achieved in two phases, mapping for area optimisation followed by new delay reduction techniques. Based on a standard set of benchmark examples, experimental results after PPR layout have shown that the proposed approach outperforms state-of-the-art approaches.
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© 1997 Springer-Verlag Berlin Heidelberg
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Lin, X., Dagless, E., Lu, A. (1997). Technology mapping of LUT based FPGAs for delay optimisation. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_229
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DOI: https://doi.org/10.1007/3-540-63465-7_229
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