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Technology mapping of heterogeneous LUT-based FPGAs

  • Maurice Kilavuka Inuani
  • Jonathan Saul
Design Tools
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)

Abstract

New techniques have been developed for the technology mapping of FPGAs containing more than one size of look-up table. The Xil inx 4000 series is one such family of devices. These have a very large share of the FPGA market, and yet the associated technology mapping problem has hardly been addressed in the literature. Our method extends the standard techniques of functional decomposition and network covering. For the decomposition, we have extended the conventional binpacking (cube-packing) algorithms so that it produces two sizes of bins. We have also enhanced it to explore several packing possibilities, and include cube division and cascading of nodes. The covering step is based on the concept of flow networks and cut-computation. We devised a theory that reduces the flow network sizes so that a dynamic programming approach can be used to compute the feasible cuts in the network. An iterative selection algorithm can then be used to compute the set cover of the network. Experimental results show good performances for the Xilinx 4K devices (about 25% improvement over MOFL and 10% over comparable algorithms in SIS in terms of CLBs).

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References

  1. 1.
    R. J. Francis, J. Rose, and K. Chung, “Chortle: A technology mapping program for lookup table-based field programmable gate arrays,” in 27th Design Automation Conference, pp. 613–619, 1990.Google Scholar
  2. 2.
    R. J. Francis, J. Rose, and Z. Vranesic, “Chortle-crf. Fast technology mapping for lookup table-based FPGAs,” in 28th Design Automation Conference, pp. 227–233, 1991.Google Scholar
  3. 3.
    R. J. Francis, J. Rose, and Z. Vranesic, “Technology mapping of lookup table-based FPGAs for performance,” in IEEE/ACM International Conference on ComputerAided Design, pp. 568–571, 1991.Google Scholar
  4. 4.
    R. Murgai, Y. Nishiza,ki, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Logic synthesis for programmable gate arrays,” in 27th Design Automation Conference, pp. 620–625, 1990.Google Scholar
  5. 5.
    R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Improved logic synthesis algorithms for table look-up architectures,” in IEEE/ACM International Conference on Computer-Aided Design, pp. 564–567, 1991.Google Scholar
  6. 6.
    R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Performance directed synthesis for table look up programmable gate arrays,” in IEEE/ACM International Conference on Computer-Aided Design, pp. 572–575, 1991.Google Scholar
  7. 7.
    P. Sawkar and D. Thomas, “Area and delay mapping for table-look-up based field programmable gate arrays,” in 29th Design Automation Conference, pp. 368–373, 1992.Google Scholar
  8. 8.
    P. Sawkar and D. Thomas, “Performance directed technology mapping for look-up table based FPGAs,” in 30th Design Automation Conference, pp. 208–212, 1993.Google Scholar
  9. 9.
    J. Cong and Y. Ding, ““flowmap”: An optimal technology mapping algorithm for delay optimization in lookup table based FPGA designs,” IEEE Trans. ComputerAided Design, vol. 13, pp. 1–12, Jan. 1994.CrossRefGoogle Scholar
  10. 10.
    K.-C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar, “DAG-Map: Graph based FPGA technology mapping for delay optimization,” IEEE Design and Test of Computers, pp. 7–20, Sept. 1992.Google Scholar
  11. 11.
    J. Cong and Y. Ding, “On nominal delay minimization in LUT-based FPGA technology mapping,” Integration-The VLSI Journal, vol. 18, pp. 73–94, 1994.CrossRefGoogle Scholar
  12. 12.
    J. Cong, Y. Ding, T. Gao, and K.-C. Chen, “An optimal performance-driven technology mapping algorithm for LUT-based FPGAs under arbitrary net-delay models,” Computers & Graphics, vol. 18, pp. 507–516, July 1994.Google Scholar
  13. 13.
    J. Cong and Y. Ding, “On area/depth trade-off in LUT-based FPGA technology mapping,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, pp. 137–148, June 1994.CrossRefGoogle Scholar
  14. 14.
    J. Cong and Y. Ding, “Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs,” in IEEE/ACM International Conference on Computer-Aided Design, pp. 110–114, 1993.Google Scholar
  15. 15.
    J. Cong and Y.-Y. Hwang, “Simultaneous depth and area minimization in LUTbased FPGA mapping,” in ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, (Monterey, California, USA), pp. 68–74, ACM, Feb. 1995.Google Scholar
  16. 16.
    K. Chung and J. Rose, “Tempt: Technology mapping for the exploration of FPGA architectures with hard-wired connections,” in 29th Design Automation Conference, (Anaheim, CA, USA), pp. 361–367, IEEE Computer Society Press, June 1992.Google Scholar
  17. 17.
    J.-Y. Lee and E. Shragowitz, “Technology mapping for FPGAs with complex block architectures by fuzzy logic technique,” in 1st Asia and South Pacific Design Automation Conference, (Japan), 1995.Google Scholar
  18. 18.
    Xilinx, The Programmable Logic Data Book. Xilinx Inc., San Jose, California, USA, 1993.Google Scholar
  19. 19.
    B. M. E. Moret and H. D. Shapiro, Algorithms from P to NP: Design and Efficiency, vol. 1. California, USA: Benjamin/Cummings Publishing Co., 1991.Google Scholar
  20. 20.
    T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. MIT Press, 1993.Google Scholar
  21. 21.
    E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A system for sequential circuit systems.“ Memorandum No. UCB/ERL M92/41, May 1992.Google Scholar
  22. 22.
    R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “MIS: A multiple-level logic optimization system,” IEEE Trans. Computer-Aided Design, vol. 6, pp. 1062–1081, Nov. 1987.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Maurice Kilavuka Inuani
    • 1
  • Jonathan Saul
    • 1
  1. 1.Programming Research GroupOxford University Computing LaboratoryParks RoadUK

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