VPR: a new packing, placement and routing tool for FPGA research

  • Vaughn Betz
  • Jonathan Rose
Design Tools
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)

Abstract

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today's industrial designs.

VPR is capable of targeting a broad range of FPGA architectures, and the source code is publicly available. It and the associated netlist translation / clustering tool VPACK have already been used in a number of research projects worldwide, and should be useful in many areas of FPGA architecture research.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    S. Brown, R. Francis, J. Rose, and Z. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.Google Scholar
  2. [2]
    Xilinx Inc., The Programmable Logic Data Book, 1994.Google Scholar
  3. [3]
    AT & T Inc., ORCA Datasheet, 1994.Google Scholar
  4. [4]
    Actel Inc., FPGA Data Book, 1994.Google Scholar
  5. [5]
    Altera Inc., Data Book, 1996.Google Scholar
  6. [6]
    V Betz and J. Rose, “Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size,” CICC, 1997, pp. 551–554.Google Scholar
  7. [7]
    S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, “Optimization by Simulated Annealing,” Science, May 13, 1983, pp. 671–680.Google Scholar
  8. [8]
    V Betz and J. Rose, “Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,” ICCAD, 1996, pp. 652–659.Google Scholar
  9. [9]
    V Betz and J. Rose, “On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs,” CSRI Tech. Rep. #358, Dept. of ECE, University of Toronto, 1996.Google Scholar
  10. [10]
    C. E. Cheng, “RISA: Accurate and Efficient Placement Routability Modeling,” DAC, 1994, pp. 690–695.Google Scholar
  11. [11]
    M. Huang, F Romeo, and A. Sangiovanni-Vincentelli, `An Efficient General Cooling Schedule for Simulated Annealing,” ICCAD, 1986, pp. 381–384.Google Scholar
  12. [12]
    W. Swartz and C. Sechen, “New Algorithms for the Placement and Routing of Macro Cells,” ICCAD, 1990, pp. 336–339.Google Scholar
  13. [13]
    J. Lam and J. Delosme, “Performance of a New Annealing Schedule,” DAC, 1988, pp. 306–311.Google Scholar
  14. [14]
    C. Ebeling, L. McMurchie, S. A. Hauck and S. Burns, “Placement and Routing Tools for the Triptych FPGA,” IEEE Trans. on VLSI, Dec. 1995, pp. 473–482.Google Scholar
  15. [15]
    C. Y. Lee, “An Algorithm for Path Connections and its Applications, “IRE Trans. Electron. Comput., Vol. EC=10, 1961, pp. 346–365.Google Scholar
  16. [16]
    J. S. Rose, W. M. Snelgrove, Z. G. Vranesic, “ALTOR: An Automatic Standard Cell Layout Program,” Canadian Conf on VLSI, 1985, pp. 169–173.Google Scholar
  17. [17]
    J. S. Rose, “Parallel Global Routing for Standard Cells,” IEEE Trans. on CAD, Oct. 1990, pp. 1085–1095.Google Scholar
  18. [18]
    S. Brown, J. Rose, Z. G. Vranesic, “A Detailed Router for Field-Programmable Gate Arrays,” IEEE Trans. on CAD, May 1992, pp. 620–628.Google Scholar
  19. [19]
    G. Lemieux, S. Brown, “A Detailed Router for Allocating Wire Segments in FPGAs,” ACMISIGDA Physical Design Workshop, 1993, pp. 215–226.Google Scholar
  20. [20]
    Y-L. Wu, M. Marek-Sadowska, “An Efficient Router for 2-D Field-Programmable Gate Arrays,”EDAC, 1994, pp. 412–416.Google Scholar
  21. [21]
    Y-L. Wu, M. Marek-Sadowska, “Orthogonal Greedy Coupling — A New Optimization Approach to 2-D FPGA Routing,” DAC, 1995, pp. 568–573.Google Scholar
  22. [22]
    M. J. Alexander, G. Robins, “New Performance-Driven FPGA Routing Algorithms,” DAC, 1995, pp. 562–567.Google Scholar
  23. [23]
    G. Lemieux, S. Brown, D. Vranesic, “On Two-Step Routing for FPGAs,” Int. Symp. on Physical Design, 1997, pp. 60–66.Google Scholar
  24. [24]
    Y-S. Lee, A. Wu, “A Performance and Routability Driven Router for FPGAs Considering Path Delays,” DAC, 1995, pp. 557–561.Google Scholar
  25. [25]
    M. J. Alexander, J. P Cohoon, J. L. Ganley, G. Robins, “Performance-Oriented Placement and Routing for Field-Programmable Gate Arrays,” EDAC, 1995, pp. 80–85.Google Scholar
  26. [26]
    S. Wilton, “Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memories,” Ph.D. Dissertation, University of Toronto, 1997.Google Scholar
  27. [27]
    S. Yang, “Logic Synthesis and Optimization Benchmarks, Version 3.0,” Tech. Report, Microelectronics Centre of North Carolina, 1991.Google Scholar
  28. [28]
    J. Cong and Y Ding, “Flowmap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,” IEEE Trans. on CAD, Jan. 1994, pp. 1–12.Google Scholar

Copyright information

© Springer-Verlag 1997

Authors and Affiliations

  • Vaughn Betz
    • 1
  • Jonathan Rose
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of Toronto TorontoCanada

Personalised recommendations