Parallel graph colouring using FPGAs

  • Barry Rising
  • Max van Daalen
  • Peter Burge
  • John Shawe-Taylor
Reconfiguration I
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1304)


In [13] a freely expandable digital architecture for feedforward neural networks was described. This architecture exploits the use of stochastic bitstreams representing real valued signals. This paper proposes a hardware implementation of a recurrent neural network to form part of a novel system for solving the graph colouring problem [5], particulary relevant to frequency assignment in mobile telecommunications systems [7].

The core elements of the design are multi-state bitstream neurons, arranged in a pipelined architecture that allow for probabilistic connections between nodes, a fixed temperature cooling schedule, and control over the degree of parallelism used in the network update rule.

We also introduce the concept of hardware paging permitting the size of graph to be unconstrained and reducing the hardware overhead.

The highly regular and compact nature of the proposed circuitry, makes it an ideal candidate for utilizing the flexibility provided by FPGA's. In such a reconfigurable system, efficient problem specific hardware is easily generated.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    E. Aarts and J. Korst. Simulated Annealing and Boltzmann Machines. John Wiley & Sons, 1989.Google Scholar
  2. 2.
    Altera Corp. FLEX8000 programmable logic device family, 1993.Google Scholar
  3. 3.
    Altera Corp. FLEX10000 embedded programmable logic device family, 1995.Google Scholar
  4. 4.
    P. Burge. Parallel pruning. in private conversation, 1996.Google Scholar
  5. 5.
    P. Burge and J Shawe-Talyor. Bitstream neurons for graph colouring. Journal of Artificial Neural Networks, pages 443–448, 1995.Google Scholar
  6. 6.
    P. Burge, J. Shawe-Talyor, and J. Zerovnik. Graph colouring by maximal evidence edge adding. presented at the Udine Workshop on Approximate Solution Of Hard Combinatorial Problems.Google Scholar
  7. 7.
    B. Chamaret, S. Ubeda, and J. Zerovnik.A randomized algorithm for graph colouring applied to channel allocation in mobile telphone networks. In Operational Research Proceedings KOI'96, pages 25–30, 1996.Google Scholar
  8. 8.
    Dimacs colouring benchmarks. available via ftp at rutgers. dimacs. edu.Google Scholar
  9. 9.
    DIMACS Research Group. Clique and Colouring Problems, A Brief Introduction. Rutgers University, December 1992.Google Scholar
  10. 10.
    A. Petford and D. Welsh. A randomised 3-colouring algorithm. In Discrete Mathematics, volume 74, pages 253–261, 1989.CrossRefGoogle Scholar
  11. 11.
    Barry Rising. Hardware design of multi-state bit stream neurons for graph colouring. Technical Report CSD-TR-96-12, Royal Holloway, June 1996.Google Scholar
  12. 12.
    J. Shawe-Taylor and J. Zerovnik. Generalised boltzmann machines. Technical Report CSD-TR-92-29, Royal Holloway, University of London, 1992.Google Scholar
  13. 13.
    M. van Daalen, P. Jeavons, and J. Shawe-Taylor. A stochastic neural architecture that exploits dynamically reconfigurable FPGAs. IEEE Workshop on FPGAS for custom computing machines, pages 202–211, 1993.Google Scholar
  14. 14.
    D. van den Bout. RIPP10 user manual, 1993.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Barry Rising
    • 1
  • Max van Daalen
    • 1
  • Peter Burge
    • 1
  • John Shawe-Taylor
    • 1
  1. 1.Department of Computer Science, Royal HollowayUniversity of LondonEghamUK

Personalised recommendations