Abstract
We developed a new micro-kernel (Tactix) that provides isochronous thread scheduling. Isochronous scheduling is designed to achieve cyclic executions of multiple threads with extremely low jitters (less than 1 msec). Furthermore, we made an experimental video-server application on top of Tactix and evaluated its performance and service quality.
The experimental VOD (video on demand) system consists of four client PCs and a video-server, and they are connected by a 10 Mbps Ethernet on which both the MPEG1 down-streams and command up-streams are transferred. Results show that the system achieves a packet loss ratio of less than 0.02 percent, without retransmission, when packet transmissions of the down-streams are controlled by the isochronous scheduler.
Preview
Unable to display preview. Download preview PDF.
References
C.L. Liu, J. Layland, “Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment,” Journal of the ACM, vol. 20, no. l, Jan. 1973.
M. Dertouzos, “Control Robotics: The Procedural Control of Physical Processes,” Proc. IFIP Cong., 1974.
L. Sha, R. Rajkumar, J.P. Lehoczky, “Priority Inheritance Protocols: An Approach to Real-Time Synchronization,” IEEE Transactions on Computers, vol. 39, no. 9, Sep. 1990.
J.K. Strosnider, J.P. Lehoczky, L. Sha, “The Deferrable Server Algorithm for Enhanced Aperiodic Responsiveness in Hard Real-Time Environments,” 0IEEE Transactions on Computers, vol. 44, no. 1, Sep. 1995.
C.W. Mercer, S. Savage, H. Tokuda, “Processor Capacity Reserves: Operating System Support for Multimedia Applications,” Proc. Intl. Conf. on Multimedia Computing and Systems (ICMCS), May 1994.
K.G. Shin, Y. Chang, “A Reservation-Based Algorithm for Scheduling Both Periodic and Aperiodic Real-Time Tasks,” IEEE Transactions on Computers, Vol. 44, No. 12, Dec. 1995.
M.B. Jones, J.S. Barrera III, A. Forin, P.J. Leach, D. Rosu, M. Rosu, “An Overview of the Rialto Real-Time Architecture,” ACM SIGOPS, Sep. 1996.
B. Ford, J. Lepreau, “Evolving Mach 3.0 to a Migrating Thread Model,” Winter Usenix, Jan. 1994.
D. Nagle, R. Uhlig, T. Mudge, S. Sechrest, “Optimal Allocation of On-chip Memory for Multiple-API Operating Systems,” IEEE, Computer Architecture News, Vo1.22, No.2, April 1994.
J. Lepreau, M. Hibler, B. Ford, J. Law, “In-Kernel Servers on Mach 3.0: Implementation and Performance,” USENIX Mach III Sytemposium, 1993.
T. Nakajima, T. Kitayama, H. Tokuda, “Experiments with Real-Time Servers in Real-Time Mach,” USENIX Mach III Symposium, 1993.
Inouye, Jon, Konuru, Ravindranath, Walpole, Jonathan, “The Effects of Virtually Address Caches on Virtual Memory Design and Performance,” SIGOPS, Vol 26, No. 4, 1992.
R. Rashid, A. Tevanian Jr., M. Young, D. Golub, R. Baron, D. Black, W. Bolosky, J. Chew, “Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures,” Proc. of ASPLOS-2, Oct. 1987.
J. Pasquale, E. Anderson, P.K. Muller, “Container Shipping: Operating System Support for I/O-Intensive Application,” IEEE COMPUTER, Mar.1994.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1997 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Iwasaki, M. et al. (1997). A micro-kernel for isochronous video-data transfer. In: Masuda, T., Masunaga, Y., Tsukamoto, M. (eds) Worldwide Computing and Its Applications. WWCA 1997. Lecture Notes in Computer Science, vol 1274. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63343-X_58
Download citation
DOI: https://doi.org/10.1007/3-540-63343-X_58
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-63343-3
Online ISBN: 978-3-540-69430-4
eBook Packages: Springer Book Archive