Architecture of cell array neuro-processor
We propose Cell Array(CA) to develop a PCA(Processing Cell Array) architecture as advocated in Reference  to improve the free degree of the composition of the instruction control unit and the memory. Also, we propose a connection method among cells to establish the architecture of the entire processor element. Our goal is to check the architecture, control sequence and it's performance. We took the back-propagation learning law as an example, because it is the typical model of the neural network.
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- 1.Morishita, T., and Teramoto, I.: Processing Cell Array Neural Network Multiprocessors proc. of IEEE International Conference on Neural Networks (1995) 1470–1473Google Scholar
- 2.Eldredge, J.G. and Hitchings, B.L.: RRANN: A Hardware Implementation of the Backpropagation Algorithm Using Reconfigur-able FPGAs. proc. of IEEE International Conference on Neural Networks (1994) 2097–2102Google Scholar
- 3.Morishita, T., Tamura, Y., Satonaka, T., Inoue, A., Katsu, S., and Otsuki, T.: A Digital Neural Network Coprocessor with a Dynamically Reconfigurable Pipeline Architecture IEICE Trans. Electron., Vol. E76-C, No. 7 (1993) 1191–1196.Google Scholar
- 4.Mauduit, N., Duranton, M., and Gobert, J.: “Lneuro 1.0: A Piece of Hardware LEGO for Building Neural Network Systems”, IEEE Trans. Neural Network, Vol. 3, No. 3 (1992) 414–422Google Scholar
- 5.Fortes, J.A.B., and Wah, W. B.: “Systolic Arrays-From Concept to Implementation”, IEEE Computer, 20, 7, (1987) 12–17.Google Scholar
- 6.Rumelhart, D.E., McClell, J.L., and the PDP Research Group: Parallel Distributed Processing. MIT Press, Cambridge, 1986.Google Scholar