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Optimizing the NAS parallel BT application for the POWER CHALLENGEarray

  • John Brown
  • Marco Zagha
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1184)

Abstract

The POWER CHALLENGEarray is a coarse-grained collection of large processor SMP nodes. This creates interesting parallelization opportunities for scalable applications. The NAS BT benchmark is a classical ADI-like application with non-trivial communication requirements. The coarse-grained distributed feature of the POWER CHALLENGEarray provides unique parallelization strategies. We explore the implementation of this benchmark on this machine and discuss the general implications for scalable application development

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References

  1. 1.
    POWER CHALLENGEarray Technical Report, PWR-CHALL-ARA-TR (1/96), Silicon Graphics, Inc.,1996.Google Scholar
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    POWER CHALLENGE Technical Report, PWR-CHALL-TR (07/94), Silicon Graphics, Inc., 1994.Google Scholar
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    D. Bailey, et al., THE NAS Parallel Benchmarks,RNR Technical Report RNR-94-007, March 1994, or see http://www.nas.nasa.gov/NAS/NPB/Specs/RNR-94-007/npbspec.html.Google Scholar
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    V. Naik, Performance of NAS Parallel Application-Benchmarks on IBM SP1, Proceeding of the Scalable High Performance Computing Conference, May 1994,pp 121–128.Google Scholar
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    J. Bruno, P.R. Cappello, Implementing the Beam and Warming Method on the Hypercube, Proceedings of 3rd Conference on Hypercube Concurrent Computers and Applications, Pasadena, CA, Jan. 19–20, 1988.Google Scholar
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    Subhash Saini and David H. Bailey, NAS Parallel Benchmark Results 12-95, Report NAS-95-021, Dec. 1995.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • John Brown
    • 1
  • Marco Zagha
    • 1
  1. 1.Silicon Graphics, Inc.Mountain View

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