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Multi-level test generation and fault diagnosis for finite state machines

  • R. Ubar
  • M. Brik
Session 6 Testing
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1150)

Abstract

In this paper, a new multi-level technique, based on alternative graphs, with uniform procedures at each level for test generation, fault simulation and fault diagnosis in finite state machines (FSM) is presented. For the description of function (behavior), structure and faults in FSM, three levels are used: functional (state transition diagrams), logical (signal path) and gate levels. In test generation, simultaneously all levels are used. Faults from different classes are inserted and activated at different levels by uniform procedures. State initialization and fault propagation are carried out only at the functional level. Backtracking will not cross level borders, hence, the high efficiency of test generation can be reached. Fault diagnosis is carried out using top-down technique, keeping the complexity of candidate fault sets in each level as low as possible.

Keywords

Boolean Function Fault Diagnosis Test Generation Fault Model Test Pattern 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Hennie F.C. Fault detecting experiments for sequential circuits. Proc. of 5th Symp. on Switching Circuit Theory and Logical Design, Princeton, N.J., Nov,1964, pp.95–110.Google Scholar
  2. [2]
    Ghosh A., Devadas S., Newton A.R. Sequential logic testing and verification. Kluwer Acad. Publish., 1992, 214 p.Google Scholar
  3. [3]
    Agrawal W.D. When to use random testing. IEEE Trans. on Computers, vol. C-27, Nov.1978,pp.l054–1055.Google Scholar
  4. [4]
    Cheng K.-T., Jou J.-Y. Functional test generation for FSMs. IEEE Int. Test Conference. 1990,pp.l62–168.Google Scholar
  5. [5]
    Grillmeyer O., Wilkinson A.J. The design and construction of a rule base and an inference engine for test system diagnosis. IEEE Int. Test Conf., 1985, pp.857–867.Google Scholar
  6. [6]
    Davis R. Diagnostic reasoning based on structure and behavior. Artificial Intelli-gence 24 (1984) 347–410.Google Scholar
  7. [7]
    Pitchumani V., Mayor P., Radia N. Fault diagnosis using functional fault model for VHDL descriptions. IEEE Int. Test Conf. Nashville, Oct., 1991, pp.327–337.Google Scholar
  8. [8]
    Ward, P.C., Armstrong, J.R. (1990). Behavioral fault simulation in VHDL. 27th ACM/IEEE Design Automation Conference, 1990, pp.587–593.Google Scholar
  9. [9]
    Ramamoorthy C.V. A structural theory of machine diagnosis. Proceedings of Spring Joint Computer Conference, 1967, pp.743–756.Google Scholar
  10. [10]
    Waicukauski J.A., Gupta V.P., Patel S.T. Diagnosis of BIST failures by PPSFP simulation. 18th IEEE International Test Conference, Washington, Sep.1987,pp.480–484.Google Scholar
  11. [11]
    Rajski J. Gemini — a logic system for fault diagnosis based on set functions. 18th Int. Symposium on Fault Tolerant Computing, Tokyo,1988, June,pp.292–297.Google Scholar
  12. [12]
    Ubar R. Test Synthesis with alternative graphs. IEEE Design & Test of Computers. Spring 1996, pp.48–57.Google Scholar
  13. [13]
    Bryant R.E. Graph-based Algorithms for Boolean Function Manipulation. IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp.667–690.Google Scholar
  14. [14]
    Ubar R., Evartson T. Optimization of fault localization procedures in computer: hardware. In “CAD in electronical and computer engineering”, Part I., Vilnius, Lithuania, 1981, pp.I75–184 (in Russian).Google Scholar
  15. [15]
    Brik M., Ubar R. Hierarchical test generation for finite state machines. Proc. of the 4th Baltic Electronics Conference. Tallinn, October 1994, pp.319–324.Google Scholar
  16. [16]
    Sallay B., Petri A., Tilly K., Pataricza A. High Level Test Pattern Generation for VHDL Circuits. IEEE European Test Workshop, Montpellier, France, June 12–14, 1996, pp. 201–205.Google Scholar
  17. [17]
    Gramatova E., Cibakova T., Bezakova J. Test Pattern Generation Algorithms on Functional/Behavioral Level. Tech. Rep. FUTEG-4/1995.Google Scholar
  18. [18]
    Gulbins M., Straube B. Applying Behavioral Level Test Generation to High-Level Design Validation. The European Design & Test Conference, Paris, March 11–14, 1996, p. 613.Google Scholar
  19. [19]
    Niermann T.M., Patel J.H. Hitec: A test generation package for sequential circuits. Proc. European Design Automation Conference, 1991, pp.214–218.Google Scholar
  20. [20]
    Ghosh A., Devadas S., Newton A.R. Test generation and verification for highly sequential circuits. IEEE Trans. on CAD, Vol.10, No.S, May 1991.Google Scholar
  21. [21]
    Thatte S.M., Abraham J.A. Test Generation for Microprocessors, IEEE Trans. Computers, Vol.29, 1980, pp.429–441.Google Scholar
  22. [22]
    Minato S. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publish., 1996, 141 p.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • R. Ubar
    • 1
  • M. Brik
    • 1
  1. 1.Tallinn Technical UniversityTallinnEstonia

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