On the yield of VLSI processors with on-chip CPU cache

  • D. Nikolos
  • H. T. Vergos
Session 5 Basic Hardware Models
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1150)


Yield enhancement through the acceptance of partially good chips is a well-known technique [1–3]. In this paper we derive a yield model for single-chip VLSI processors with a partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area and various manufacturing process parameters as defect densities and the fault clustering parameter.

Indexing terms

On-chip CPU caches Partially good chips Yield Enhancement Fault Tolerance 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Koren I. and Singh A.D., “Fault Tolerance in VLSI Circuits”, IEEE Computer, pp. 73–83, July 1990.Google Scholar
  2. [2]
    Stapper C. H., Mc Laren A. N. and Dreckmann M., “Yield Model for Productivity Optimization of VLSI Memory Chips with redundancy and Partially Good Product”, IBM Journal of Research and Development, Vol. 20, 1980, pp. 398–409.Google Scholar
  3. [3]
    Stapper C. H., “Block Alignment: A Method for Increasing the Yield of Memory Chips that are Partially Good”, Defect and Fault Tolerance in VLSI Systems, I. Koren (ed.), pp. 243–255, New York: Plenum, 1989.Google Scholar
  4. [4]
    “PowerPC 601 — RISC Microprocessor User's Manual” Motorola Semiconductor Ttechnical Data Book, Motorola 1993.Google Scholar
  5. [5]
    Miraburi S. at. al., “ The MIPS R4000 Processor”, IEEE Micro, April 1992, pp. 10–22.Google Scholar
  6. [6]
    Edmodson J. H. et. al., “ Superscalar Instruction Execution in the 21164 Alpha Microprocessor”, IEEE Micro, April 1995, pp. 33–43.Google Scholar
  7. [7]
    Sohi G., “Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors”, IEEE Transactions on Computers, vol. 38, no. 4, pp. 484–492, April 1989.Google Scholar
  8. [8]
    Pour A. F. and Hill M. D., “Performance Implications of Tolerating Cache Faults”, IEEE Transactions on Computers, vol. 42, no. 3, pp. 257–267, March 1993.Google Scholar
  9. [9]
    Koren I., Koren Z. and Pradhan D. K., “Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay”, IEEE Journal of Solid-State Circuits, Vol. 23, No. 3, pp. 859–865, June 1988.Google Scholar
  10. [10]
    Koren I. and Stapper C. H., “Yield Models for Defect-Tolerant VLSI Circuits: A review”, Defect and Fault Tolerance in VLSI Systems, Vol. 1, Koren, ed., Plenum, New York, pp. 1–21, 1989.Google Scholar
  11. [11]
    Wilton S. J. E. and Jouppi N. P., “An Enhanced Access and Cycle Time Model for On-Chip Caches”, DEC Western Research Lab, Tech Report 93/5.Google Scholar
  12. [12]
    Mulder J. M., Quach N. T. and Flynn M. J., “An Area Model for On-Chip Memories and its Application”, IEEE J. of Solid-State Circuits, 26, 2, pp. 98–106, Feb. 1991.Google Scholar
  13. [13]
    Gallup M. G., et. al., “Testability Features of the 68040”, in Proc. of International Test Conference, Washington DC, USA, 10–14 September, 1990, pp. 749–757.Google Scholar
  14. [14]
    Saxena N. R., et. al., “Fault-Tolerant Features in the HaL Memory Management Unit”, IEEE Transactions on Computers, Vol. 44, No. 2, pp. 170–179, February 1995.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • D. Nikolos
    • 1
  • H. T. Vergos
    • 1
  1. 1.Department of Computer Engineering and InformaticsUniversity of PatrasRioGreece

Personalised recommendations