Fault injection evaluation of assigned signatures in a RISC processor

  • Pedro Furtado
  • Henrique Madeira
Session 2 Fault Injection
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1150)

Abstract

This paper proposes a new assigned signature monitoring technique called VASC (Versatile Assigned Signature Checking) and presents a fault injection evaluation of this technique in a modern reduced instruction set processor (RISC). VASC is applied at the machine instructions level and is the very first assigned signature monitoring technique that allows the user to choose block sizes and checking intervals with complete freedom. This feature allows the tuning of the application with the lowest overhead and makes it possible to identify and analyse the relationship between overheads and coverages for different choices of block sizes and checking intervals. Previous works presented assigned signature techniques that were either specific to a Very Large Instruction Word (VLIW) processor or have very high memory and execution time overhead. VASC can be applied to any system with small (and adjustable) execution time and memory overhead. We have measured those overheads in a PowerPC processor and in a Transputer T805 processor, showing that they are completely adjustable. One interesting conclusion is that the best error coverage of the technique does not correspond to the highest amount of control flow checking. The evaluation of the error coverage and latency of VASC, implemented in a PowerPC RISC processor, has been carried out by using the Xception software fault injection tool. The technique accounted for 10 to 16% of the detected errors, but the overall error coverage improvement was relatively small (less than 4%). One reason for this is in the fact that the percentage of control flow errors (the main type of errors detected by VASC) in the PowerPC is relatively low compared to the same percentage in processors with a more complex instruction set, which suggests that assigned signatures are much better suited for systems having variable-sized instructions and less efficient memory access checking.

Keywords

Fault Injection Control Flow Graph Memory Overhead Block Graph RISC Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Pedro Furtado
    • 1
  • Henrique Madeira
    • 1
  1. 1.University of CoimbraPortugal

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