Fault injection evaluation of assigned signatures in a RISC processor

  • Pedro Furtado
  • Henrique Madeira
Session 2 Fault Injection
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1150)


This paper proposes a new assigned signature monitoring technique called VASC (Versatile Assigned Signature Checking) and presents a fault injection evaluation of this technique in a modern reduced instruction set processor (RISC). VASC is applied at the machine instructions level and is the very first assigned signature monitoring technique that allows the user to choose block sizes and checking intervals with complete freedom. This feature allows the tuning of the application with the lowest overhead and makes it possible to identify and analyse the relationship between overheads and coverages for different choices of block sizes and checking intervals. Previous works presented assigned signature techniques that were either specific to a Very Large Instruction Word (VLIW) processor or have very high memory and execution time overhead. VASC can be applied to any system with small (and adjustable) execution time and memory overhead. We have measured those overheads in a PowerPC processor and in a Transputer T805 processor, showing that they are completely adjustable. One interesting conclusion is that the best error coverage of the technique does not correspond to the highest amount of control flow checking. The evaluation of the error coverage and latency of VASC, implemented in a PowerPC RISC processor, has been carried out by using the Xception software fault injection tool. The technique accounted for 10 to 16% of the detected errors, but the overall error coverage improvement was relatively small (less than 4%). One reason for this is in the fact that the percentage of control flow errors (the main type of errors detected by VASC) in the PowerPC is relatively low compared to the same percentage in processors with a more complex instruction set, which suggests that assigned signatures are much better suited for systems having variable-sized instructions and less efficient memory access checking.


Fault Injection Control Flow Graph Memory Overhead Block Graph RISC Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    A. Aho, R. Sethi, and J. Ulman, “Compilers: principles, techniques, and tools”, Addison-Wesley Ed., 1985.Google Scholar
  2. [2]
    Carreira, J., H. Madeira and João Gabriel Silva “Xception:Software Fault Injection and Monitoring in Processor Functional Units”. Procs. 5th Conference on Dependable Computing for Critical Applications, Urbana-Champaign, IL, USA, Sept 27–29,1995.Google Scholar
  3. [3]
    Gunneflo, U., J. Karsson and J. Torin, “Evaluation of Error Detection Schemes Using Fault Injection by Heavy-ion Radiation”, Procs. 19th FTCS, pp.340–347, 1989.Google Scholar
  4. [4]
    Madeira,H., M. Rela,P. Furtado and J. G. Silva “Time Behaviour monitoring as an Error Detection Mechanism”. Conf. on Dependable Computing for Critical Applications DCCA-3 Sept-92Google Scholar
  5. [5]
    Madeira, H. and J. Gabriel Silva “On-Line Signature Learning and Checking”. Conference on Dependable Computing for Critical Applications, Springer-Verlag, J. Meyer and R. Schlichting (eds.) 1992 pp 394–420.Google Scholar
  6. [6]
    Mahmood, A. and E. McCluskey. Watchdog Processors — Error Coverage and Overhead. Proc. of the 15th Symposium on Fault Tolerant Computing, Ann Arbor, Michigan, USA, June 1985, pp 214–219.Google Scholar
  7. [7]
    Mahmood, A. and E. McCluskey. Concurrent Error Detection using Watchdog Processors — A Survey. IEEE Trans. on Computers, Vol37, pp 160–174, Feb 1988.Google Scholar
  8. [8]
    Miremadi, G., J. Karlsson,U. Gunneflo, J. Torin, “Two Software Techniques for On-line Error Detection”. Procs. of 22th Symp. on Fault Tolerant Computing, 1992.Google Scholar
  9. [9]
    Miremadi, G., J. Ohlsson, M. Rimém, J. Karlsson, “Use of Time and Address Signatures for Control Flow Checking”. Conference on Dependable Computing for Critical Applications (DCCA 5), Urbana-Champaign, USA, Sept. 95, pp 113–124.Google Scholar
  10. [10]
    Namjoo, M. “Techniques for Concurrent Testing of VLSI Processor Operation”. Proceedings of Int. Test Conf., Philadelphia, Nov.15–18 1982, p.461–468.Google Scholar
  11. [11]
    Ohlssom, J., M. Rimen,U. Gunneflo, A Study of Transient Fault-Injection into a 32-bit RISC with Watchdog, Proceedings of the 22th Fault Tolerant Computing Symposium, 1992,pp. 316–325.Google Scholar
  12. [12]
    Ohlsson, J., M. Rimén, “Implicit Signature Checking” Proc. of 25th Symposium on Fault Tolerant Computing, FTCS-25, Jun 95.Google Scholar
  13. [13]
    Saxena, N. R. and E. J. McCluskey, “ Control Flow Checking Using Watchdog Assists and Extended Precision Checksums” IEEE Transactions on Computers Vol 39, n∘4, April 1990.Google Scholar
  14. [14]
    Shen, J. P. and M. A. Shuette “On-line self-monitoring using signatured instruction streams”, International Test Conference, ITC83,pp 275–282,1983.Google Scholar
  15. [15]
    Shuette, M. and J. Shen. “Processor Control Flow Monitoring using Signatured Instruction Steams”. IEEE Trans. on Computers, Vol 36, pp 264–275, March 1987.Google Scholar
  16. [16]
    Shuette, M. and J. P. Shen. Exploiting Instruction-level Resource Parallelism for Transparent, Integrated Control-flow Monitoring. Proc.of 21th Symposium on Fault Tolerant Computing, IEEE FTCS 21, 318–325, 1991.Google Scholar
  17. [17]
    Sosnowski, J., “Transient fault tolerance in microprocessor controllers”, Hardware and Software for real time process control, J. Zalewski and W. Ehrenberger (eds.), Elsevier Science Publishers B. V. (North Holland), IFIP, 1989, pp. 189–195.Google Scholar
  18. [18]
    Warter, N. J. and W. W. Hwu, “A software based approach to achieving optimal performance for signature control flow checking”, Proceedings of 20th Symposium on Fault Tolerant Computing, FTCS-20, 1991, pp. 442–449.Google Scholar
  19. [19]
    Wilken, K. and J. P. Shen, “Continous Signature Monitoring: Low-Cost Concurrent Detection of Processor Control Erros”, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 6, June 1990, p. 629–641.Google Scholar
  20. [20]
    Wilken, K. and J. Shen. Continuous Signature Monitoring: Efficient Concurrent Error-detection of Processor Control Errors. IEEE 18th International Test Conference.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Pedro Furtado
    • 1
  • Henrique Madeira
    • 1
  1. 1.University of CoimbraPortugal

Personalised recommendations