Abstract
We present the design of the Hades coprocessor board, which uses the new XC6200 FPGA family from Xilinx. The board contains a single XC6216 with 64×64 cells and 256 KB of fast local memory. It is accessed from the host (an ETH Ceres-2 workstation) via a conventional memory interface. A complete listing of the logic necessary to interface the XC6216 FPGA is presented in the Lola HDL. Especially for readers new to the field of hardware design, we report on our experiences during the development of the board.
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Ludwig, S.H.M. (1996). The design of a coprocessor board using Xilinx's XC6200 FPGA — An experience report. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_8
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DOI: https://doi.org/10.1007/3-540-61730-2_8
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