An EPLD based transient recorder for simulation of video signal processing devices in a VHDL environment close to system level conditions
An EPLD based low cost transient recorder of video signal bandwidth (sampling rate 25 M Hz) is presented. It will be used to record and replay video signals. These video signals are handled by a video processing unit, under construction in a VHDL environment. The main advantage of this self made transient recorder is that the video signal processing device, which is under construction in a VHDL environment, uses the same analog components as the EPLD based transient recorder. Thus, the video signal passes the same signal path and components in the final device. This results in a simulation environment very close to the final system environment.
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