Abstract
A concurrent design and evaluation environment for an FPGA and its CAD system is presented. By describing an FPGA architecture in a description language, the user can evaluate it, e.g., switch pattern in a switch box and routing resource balance. In addition, this environment has a middle-ware which enables users to develop dedicated CAD systems rapidly. While they are evaluating their FPGAs, they can obtain original CAD tool sets before the FPGAs are manufactured. This is the best way to realize a well-balanced FPGA and its CAD system. This paper overviews the system and introduces some examples.
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Tsutsui A., Miyazaki T., Yamada K., and Ohta N., “ Special Purpose FPGA for High-speed Digital Telecommunication Systems”, Proc. ICCD'95, pp. 486–491, October 1995.
Amerson R., Carter R.J., Culbertson W.B., Kuekes P., and Snider G., “Teramac — Configurable Custom Computing,” Proc. FCCM'95, pp. 32–38, Napa CA, April 1995.
Brown S.D., Francis R.J., Rose J. and Vranesic Z.G., “Field-Programmable Gate Arrays,” Kluwer Academic Publishers, 1992.
Takashima Y., Takahashi A., and Kajitani Y., “Detailed-Routability of FPGAs with Extremal Switch-Block Structures,” Proc. ED&TC'96, Paris, March 1996.
Albaharna O.T., Cheung P.Y.K., and Clarke T.J., “Area & Time Limitations of FPGA-based Virtual Hardware,” Proc. ICCD'94, pp. 184–189, October 1994.
Xilinx Inc., “XACT Reference Guide, Volume III,” 1994.
Zuken Inc., “CR-5000 Brochure,” 1994.
Xilinx Inc., “The Field Programmable Gate Array Data Book,” 1994.
Tsutsui A., and Miyazaki T., “An Efficient Design Environment and Algorithms for Transport Processing FPGA,” Proc. VLSI'95, pp. 791–798, August 30–September 1 1995.
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© 1996 Springer-Verlag Berlin Heidelberg
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Miyazaki, T., Tsutsui, A., Ishii, K., Ohta, N. (1996). FACT: Co-evaluation environment for FPGA architecture and CAD system. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_4
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DOI: https://doi.org/10.1007/3-540-61730-2_4
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