Abstract
This paper compares schematic-based FPGA design with design based on logic synthesis. We show that, unlike in ASIC design, using logic synthesis does not result in inferior designs for FPGAs. This is due to the importance of logic optimization in FPGA design, where tools such as Synopsys implement more powerful algorithms than those implemented by FPGA vendor supplied software.
We also show how to make the transition from a schematic-based to a synthesis-based environment and how to leverage schematic designs.
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Gschwind, M., Mautner, C. (1996). Migration from schematic-based designs to a VHDL synthesis environment. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_37
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DOI: https://doi.org/10.1007/3-540-61730-2_37
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