Growable FPGA macro generator
Because FPGA designs have routing delays that can be larger than logic-cell delays, it is important to generate optimum designs for different macros. This paper describes an FPGA macro generator for growable macro designs using the IBM FPGA architecture. The IBM Macro Generator (MacGen) automatically creates the optimum designs in terms of higher performance and fewer logic-cell counts. Its output includes physical design layout, CAE front-end models and, for schematic users, macro symbols. An automatic place-and-route tool will implement the macro as generated when it is encountered in a netlist. Currently, 17 different macro types can be generated using MacGen.
Present methodologies supported with MacGen are ViewLogic Powerview™ and ProSeries™ schematic entry and simulation; Synopsys FPGA Compiler™ synthesis, and Cadence Verilog-XL™ or MTI V-System™ VHDL simulation; IBM Booledozer™ synthesis and MTI V-System™ VHDL simulation. Netlists from these supported front-end tools flow to the IBM FPGA design system for automatic place-and-route, completing the design of the device.
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