Implementing reconfigurable datapaths in FPGAs for adaptive filter design

Abstract

Realizing adaptive digital filters is most easily done in programmable logic devices, since the coefficients and the filter structure can be varied through reconfiguration of the device, whose architecture has a significant impact on the performance. A symmetrical, fine-grained FPGA enables design techniques like pipelining and bit-serial processing and still allows for a simple, VHDL-based design flow with predictable timing. The implementation of a 8-tap, 8-bit FIR filter is shown as an example. Using bit-serial processing, the sample rate can exceed 5MHz.