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FPGA implementation of the block-matching algorithm for motion estimation in image coding

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Part of the Lecture Notes in Computer Science book series (LNCS,volume 1142)

Abstract

In this paper we describe an FPGA implementation of a previously proposed architecture that performs motion estimation in image coding using the full-search Block-Matching algorithm. The emphasis of this work is to evaluate the suitability of this technology to solve the motion estimation problem (one of the most demanding parts of the image coding process). The result is a two-FPGA implementation that performs at 925 MOPS.

Keywords

  • Motion Estimation
  • Clock Frequency
  • Search Area
  • Image Code
  • FPGA Implementation

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© 1996 Springer-Verlag Berlin Heidelberg

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Sanz, C., de Zulueta, L., Meneses, J.M. (1996). FPGA implementation of the block-matching algorithm for motion estimation in image coding. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_15

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  • DOI: https://doi.org/10.1007/3-540-61730-2_15

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61730-3

  • Online ISBN: 978-3-540-70670-0

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