In this paper we describe an FPGA implementation of a previously proposed architecture that performs motion estimation in image coding using the full-search Block-Matching algorithm. The emphasis of this work is to evaluate the suitability of this technology to solve the motion estimation problem (one of the most demanding parts of the image coding process). The result is a two-FPGA implementation that performs at 925 MOPS.
Keywords
- Motion Estimation
- Clock Frequency
- Search Area
- Image Code
- FPGA Implementation
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