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Stochastic methods for transistor size optimization of CMOS VLSI circuits

  • Robert Rogenmoser
  • Hubert Kaeslin
  • Tobias Blickle
Applications of Evolutionary Computation Evolutionary Computation in Electrical, Electronics, and Communications Engineering
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1141)

Abstract

The performance of a CMOS circuit depends heavily on its transistor sizes. We have tested a standard optimizer, a Monte Carlo scheme and a method based on Genetic Algorithms combined with very accurate SPICE simulations to automatically optimize transistor sizes of three different digital CMOS circuits. While the standard optimizer and the Monte Carlo scheme are advantageous for small circuits, the method based on Genetic Algorithms was found to be more stable for larger circuits.

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References

  1. [Bäc92]
    Thomas Bäck. GENEsYs, 1992. Computer Science Department, LSXI, University of Dortmund, Baroper Str. 301, D-4600 Dortmund 50, Germany.Google Scholar
  2. [Bäc94]
    Thomas Bäck. Evolutionary Algorithms in Theory and Practice. PhD thesis, Fachbereich Informatik, Universität Dortmund, 1994.Google Scholar
  3. [Heu90]
    L. S. Heusler. Transistor Sizing for Timing Optimization of Combinational Digital CMOS Circuits. PhD thesis, ETH Zürich, 1990.Google Scholar
  4. [HK94]
    A. M. Hill and S-M. Kang. Genetic Algorithm Based Design Optimization of CMOS VLSI Circuits. In Proceedings of the Third International Conference on Parallel Problem Solving from Nature — PPSN III, pages 546–555, October 1994.Google Scholar
  5. [Hsp]
    HSPICE — Circuit Simulator, Metasoft.Google Scholar
  6. [MSV93a]
    Heinz Mühlenbein and Dirk Schlierkamp-Voosen. Predictive models for the breeder genetic algorithm. Evolutionary Computation, 1(1), 1993.Google Scholar
  7. [MSV93b]
    Heinz Mühlenbein and Dirk Schlierkamp-Voosen. The science of breeding and its application to the breeder genetic algorithm. Evolutionary Computation, 1(4), 1993.Google Scholar
  8. [RH95]
    R. Rogenmoser and Q. Huang. A 375 MHz 1-Μm CMOS 8-Bit Multiplier. In Proceedings of the 1995 Symposium on VLSI Circuits, pages 13–14, June 1995.Google Scholar
  9. [RH96]
    R. Rogenmoser and Q. Huang. An 800-MHz 1-Μm CMOS Pipelined 8-bit Adder using True Single-Phase Clocked Logic-Flip-Flops. IEEE Journal of Solid-State Circuits, 31(3):401–409, March 1996.CrossRefGoogle Scholar
  10. [Sah64]
    C. T. Sah. Characteristics of the Metal-Oxide-Semiconductor Transistors. IEEE Transactions on Electron Devices, ED-11:324–345, July 1964.Google Scholar
  11. [Sch81]
    H.-P. Schwefel. Numerical Optimization of Computer Models. Wiley, Chichester, 1981.Google Scholar
  12. [Sys89]
    Gilbert Syswerda. Uniform crossover in genetic algorithms. In J. David Schaffer, editor, Proceedings of the Third International Conference on Genetic Algorithms, pages 2–9, San Mateo, CA, 1989. Morgan Kaufmann Publishers.Google Scholar
  13. [Whi89]
    Darrell Whitley. The GENITOR algorithm and selection pressure: Why rank-based allocation of reproductive trials is best. In J. David Schaffer, editor, Proceedings of the Third International Conference on Genetic Algorithms, pages 116–121, San Mateo, CA, 1989. Morgan Kaufmann Publishers.Google Scholar
  14. [Wur93]
    L. T. Wurtz. An Efficient Scaling Procedure for Domino CMOS Logic. IEEE Journal of Solid-State Circuits, 28(9):979–982, September 1993.CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Robert Rogenmoser
    • 1
  • Hubert Kaeslin
    • 1
  • Tobias Blickle
    • 2
  1. 1.Integrated Systems LaboratorySwitzerland
  2. 2.Computer Engineering and Networks LaboratoryETH ZürichZürichSwitzerland

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