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Learning heuristics for OBDD minimization by Evolutionary Algorithms

  • Rolf Drechsler
  • Nicole Göckel
  • Bernd Becker
Applications of Evolutionary Computation Evolutionary Computation in Machine Learning, Neural Networks, and Fuzzy Systems
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1141)

Abstract

Ordered Binary Decision Diagrams (OBDDs) are the state-of-the-art data structure in CAD for ICs. OBDDs are very sensitive to the chosen variable ordering, i.e. the size may vary from linear to exponential.

In this paper we present an Evolutionary Algorithm (EA) that learns good heuristics for OBDD minimization starting from a given set of basic operations. The difference to other previous approaches to OBDD minimization is that the EA does not solve the problem directly. Rather, it developes strategies for solving the problem.

To demonstrate the efficiency of our approach experimental results are given. The newly developed heuristics are more efficient than other previously presented methods.

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References

  1. 1.
    P. Ashar, S. Devadas, and K. Keutzer. Gate-delay-fault testability properties of multiplexor-based networks. In Int'l Test Conf., pages 887–896, 1991.Google Scholar
  2. 2.
    P. Ashar, S. Devadas, and K. Keutzer. Path-delay-fault testability properties of multiplexor-based networks. Integration the VLSI Jour., 15(1):1–23, 1993.CrossRefGoogle Scholar
  3. 3.
    T. Bäck and H. Schwefel. An overview of evolutionary algorithms for parameter optimization. Evolutionary Computation, 1(1):1–23, 1993.Google Scholar
  4. 4.
    B. Bollig, M. Löbbing, and I. Wegener. Simulated annealing to improve variable orderings for OBDDs. In Int'l Workshop on Logic Synth., pages 5b:5.1–5.10, 1995.Google Scholar
  5. 5.
    B. Bollig, P. Savicky, and I. Wegener. On the improvement of variable orderings for OBDDs. IFIP Workshop on Logic and Architecture Synthesis, Grenoble, pages 71–80, 1994.Google Scholar
  6. 6.
    R.E. Bryant. Graph — based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 8:677–691, 1986.Google Scholar
  7. 7.
    R.E. Bryant. Symbolic boolean manipulation with ordered binary decision diagrams. ACM, Comp. Surveys, 24:293–318, 1992.Google Scholar
  8. 8.
    L. Davis. Handbook of Genetic Algorithms. van Nostrand Reinhold, New York, 1991.Google Scholar
  9. 9.
    R. Drechsler and B. Becker. Learning heuristics by genetic algorithms. In ASP Design Automation Conf., pages 349–352, 1995.Google Scholar
  10. 10.
    R. Drechsler, B. Becker, and N. Göckel. A genetic algorithm for minimization of Fixed Polarity Reed-Muller expressions. In Int'l Conf. on Artificial Neural Networks and Genetic Algorithms, pages 392–395, 1995.Google Scholar
  11. 11.
    R. Drechsler, B. Becker, and N. Göckel. A genetic algorithm for variable ordering of OBDDs. In Int'l Workshop on Logic Synth., pages P5c:5.55–5.64, 1995.Google Scholar
  12. 12.
    H. Esbensen. A macro-cell global router based on two genetic algorithms. In European Design Automation Conf., pages 428–433, 1994.Google Scholar
  13. 13.
    S.J. Friedman and K.J. Supowit. Finding the optimal variable ordering for binary decision diagrams. In Design Automation Conf., pages 348–356, 1987.Google Scholar
  14. 14.
    H. Fujii, G. Ootomo, and C. Hori. Interleaving based variable ordering methods for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 38–41, 1993.Google Scholar
  15. 15.
    M. Fujita, H. Fujisawa, and N. Kawato. Evaluation and improvements of boolean comparison method based on binary decision diagrams. In Int'l Conf. on CAD, pages 2–5, 1988.Google Scholar
  16. 16.
    M. Fujita, H. Fujisawa, and Y. Matsunaga. Variable ordering algorithms for binary decision diagrams and their evolution. IEEE Trans. on CAD, 12:6–12, 1993.Google Scholar
  17. 17.
    M. Fujita, Y. Matsunga, and T. Kakuda. On variable ordering of binary decision diagrams for the application of multi-level synthesis. In European Conf. on Design Automation, pages 50–54, 1991.Google Scholar
  18. 18.
    D.E. Goldberg. Genetic Algortithms in Search, Optimization & Machine Learning. Addision-Wesley Publisher Company, Inc., 1989.Google Scholar
  19. 19.
    N. Ishiura, H. Sawada, and S. Yajima. Minimization of binary decision diagrams based on exchange of variables. In Int'l Conf. on CAD, pages 472–475, 1991.Google Scholar
  20. 20.
    A. Kuehlmann and L.P.P.P. van Ginneken. Grammar-based optimization of synthesis scenarios. In Int'l Conf. on Comp. Design, pages 20–25, 1994.Google Scholar
  21. 21.
    L. Lavagno, P. McGeer, A. Saldanha, and A.L. Sangiovanni-Vincentelli. Timed shannon circuits: A power-efficient design style and synthesis tool. In Design Automation Conf., pages 254–260, 1995.Google Scholar
  22. 22.
    V.V. Le, T. Besson, A. Abbara, D. Brasen, H. Bogushevitsh, G. Saucier, and M. Crastes. ASIC prototyping with area oriented mapping for ALTERA/FLEX devices. In SASIMI, pages 176–183, 1995.Google Scholar
  23. 23.
    J. Lienig and K. Thulasiraman. A genetic algorithm for channel routing in VLSI circuits. Evolutionary Computation, 1(4):293–311, 1993.Google Scholar
  24. 24.
    S. Malik, A.R. Wang, R.K. Brayton, and A.L. Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In Int'l Conf. on CAD, pages 6–9, 1988.Google Scholar
  25. 25.
    S. Minato, N. Ishiura, and S. Yajima. Shared binary decision diagrams with attributed edges for efficient boolean function manipulation. In Design Automation Conf., pages 52–57, 1990.Google Scholar
  26. 26.
    R. Murgai, Y. Nishizaki, N. Shenoy, R.K. Brayton, and A. Sangiovanni-Vincentelli. Logic synthesis for programmable gate arrays. In Design Automation Conf., pages 620–625, 1990.Google Scholar
  27. 27.
    S. Panda and F. Somenzi. Who are the variables in your neighborhood. In Int'l Conf. on CAD, pages 74–77, 1995.Google Scholar
  28. 28.
    D.E. Ross, K.M. Butler, R. Kapur, and M.R. Mercer. Functional approaches to generating orderings for efficient symbolic representations. In Design Automation Conf., pages 624–627, 1992.Google Scholar
  29. 29.
    R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 42–47, 1993.Google Scholar
  30. 30.
    S. Yang. Logic synthesis and and optimization benchmarks user guide. Technical Report 1/95, Microelectronic Center of North Carolina, Jan. 1991.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • Rolf Drechsler
    • 1
  • Nicole Göckel
    • 1
  • Bernd Becker
    • 1
  1. 1.Institute of Computer ScienceAlbert-Ludwigs-UniversityFreiburg im BreisgauGermany

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