Advertisement

An analog CMOS neural network with on-chip learning and multilevel weight storage

  • M. Conti
  • G. Guaitini
  • C. Turchetti
Poster Presentations 2 Implementations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1112)

Abstract

An analog neural network with four neurons and 16 synapses, fabricated in a 1.2 μm n-well single-polysilicon, double-metal process, is presented. The circuit solutions adopted, for on-chip learning and weight storage, particularly simple and silicon area-efficient, are capable of solving the main problems to the implementation of analog neural networks.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Y.Arima et al., “A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40k Synapses”, IEEE J. Solid-State Circuits, p. 1854, Vol. 27, Dec. 1992, No. 17.Google Scholar
  2. [2]
    B.L.Barranco et al., “Modular Analog Continuous-Time VLSI Neural Networks with On-Chip Hebbian Learning and Analog Storage”, IEEE ISCAS '92, S. Diego, 10–13 May 1992.Google Scholar
  3. [3]
    T.Morie, Y.Amemiya, “An All-Analog Expandable Neural Network LSI with On-Chip Back-Propagation Learning”, IEEE J. Solid State Circuits, Vol. 29, No. 9, September 1994, pp.1086–1093.B17.Google Scholar
  4. [4]
    Y.K.Choi, S.Y.Lee, “Subthreshold MOS Implementation of Neural Networks with On-Chip Error Back-Propagation Learning”, Proc. of I J.C.N.N., 1993, pp. 849–852.Google Scholar
  5. [5]
    M.R.Belli, M.Conti, C.Turchetti, “Analog Brownian Weight Movement for Learning of Artificial Neural Networks”, Proc. of the European Symposium on Artificial Neural Networks ESANN'95, Brussels, p.75–80, April 19–21 1995.Google Scholar
  6. [6]
    A.Papoulis, “Probability, random variables, and stochastic processes”, McGraw-Hill, New York, 1965.Google Scholar
  7. [7]
    M.Conti, S.Orcioni, C.Turchetti, “A Class of Neural Networks Based on Approximate Identity for Analog IC's Implementation”, IEICE Trans. on Fundamentals, Japan, Vol. E77-A, No. 6, June 1994, pp. 1069–1079.Google Scholar
  8. [8]
    M.H.Cohen, A.G.Andreou, “Current-Mode Subthreshold MOS Implementation of the Herault-Jutten Autoadaptive Network”, IEEE J. Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 714–727.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • M. Conti
    • 1
  • G. Guaitini
    • 1
  • C. Turchetti
    • 1
  1. 1.Dept. of ElectronicsUniv. of AnconaAnconaItaly

Personalised recommendations