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MDG tools for the verification of RTL designs

  • K. D. Anon
  • N. Boulerice
  • E. Cerny
  • F. Corella
  • M. Langevin
  • X. Song
  • S. Tahar
  • Y. Xu
  • Z. Zhou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1102)

References

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    Randal E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677–691, August 1986.Google Scholar
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    J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design, 13(4):401–424, April 1994.CrossRefGoogle Scholar
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    F. Corella, Z. Zhou, X. Song, M. Langevin, and E. Cerny. Multiway decision graphs for automated hardware verification. To appear in the journal Formal Methods in System Design. Available as IBM technical report RC19676.Google Scholar
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    F. Corella, M. Langevin, E. Cerny, Z. Zhou and X. Song. State enumeration with abstract descriptions of state machines. In Proc. of IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (Charme'95). October, 1995, Frankfurt, Germany.Google Scholar
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    S. Tahar, Z. Zhou, X. Song, E. Cerny and M. Langevin. Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. In IEEE Proc. of Sixth Great Lakes Symposium on VLSI. Iowa, USA, March, 1996.Google Scholar
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    The home page of the multi-site MDG verification group: http://www.iro.umontreal.ca/labs/lasso/research/mdgverif/mdgverif_eng.html.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • K. D. Anon
    • 1
  • N. Boulerice
    • 1
  • E. Cerny
    • 1
  • F. Corella
    • 2
  • M. Langevin
    • 3
  • X. Song
    • 1
  • S. Tahar
    • 1
  • Y. Xu
    • 1
  • Z. Zhou
    • 1
  1. 1.D'IROUniversité de MontréalCanada
  2. 2.Hewlett-Packard CompanyUSA
  3. 3.GMD-SETGermany

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