A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits

  • Fulvio Corno
  • Paolo Prinetto
  • Maurizio Rebaudengo
  • Matteo Sonza Reorda
Conference paper

DOI: 10.1007/3-540-61142-8_583

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1067)
Cite this paper as:
Corno F., Prinetto P., Rebaudengo M., Reorda M.S. (1996) A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits. In: Liddell H., Colbrook A., Hertzberger B., Sloot P. (eds) High-Performance Computing and Networking. HPCN-Europe 1996. Lecture Notes in Computer Science, vol 1067. Springer, Berlin, Heidelberg

Abstract

The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements.

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Copyright information

© Springer-Verlag 1996

Authors and Affiliations

  • Fulvio Corno
    • 1
  • Paolo Prinetto
    • 1
  • Maurizio Rebaudengo
    • 1
  • Matteo Sonza Reorda
    • 1
  1. 1.Dip. di Automatica e InformaticaPolitecnico di TorinoTorinoItaly

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