A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits

  • Fulvio Corno
  • Paolo Prinetto
  • Maurizio Rebaudengo
  • Matteo Sonza Reorda
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1067)

Abstract

The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [ACAg88]
    V.D. Agrawal, K.-T. Cheng, P. Agrawal, “CONTEST: A Concurrent Test Generator for Sequential Circuits,” Proc. 25th Design Automation Conference, 1988, pp. 84–89Google Scholar
  2. [BBKo89]
    F. Brglez, D. Bryant, K. Kozminski, “Combinational profiles of sequential benchmark circuits,” Proc. Int. Symp. on Circuits And Systems, 1989, pp. 1929–1934Google Scholar
  3. [CHSo93]
    H. Cho, G.D. Hatchel, F. Somenzi, “Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration,” IEEE Trans. on CAD/ICAS, Vol. CAD-12, No. 7, pp. 935–945, 1993Google Scholar
  4. [CPRS95]
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva, “A PVM Tool for Automatic Test Generation on Parallel and Distributed Systems,” Proc. Int. Conf. on High-Performance Computing and Networking, Milan (Italy), 1995, pp. 39–44Google Scholar
  5. [GBDJ93]
    A. Geist, A. Beguelin, J. Dongarra, W. Jiang, R. Manchek, V. Sunderam, “PVM 3 User's Guide and Reference Manual,” Oak Ridge Nat. Lab., Internal Report ORNL/TM-12187, 1993Google Scholar
  6. [Gold89]
    D.E. Goldberg, “Genetic Algorithms in Search, Optimization, and Machine Learning,” Addison-Wesley, 1989Google Scholar
  7. [NiPa91]
    T. Niermann, J.H. Patel, “HITEC: A Test Generator Package for Sequential Circuits,” Proc. European Design Automation Conf., 1991, pp. 214–218Google Scholar
  8. [PRSR94]
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, “An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms,” Proc. Int. Test Conf., 1994, pp. 240–249Google Scholar
  9. [RPGN94]
    E.M. Rudnick, J.H. Patel, G.S. Greenstein, T.M. Niermann, “Sequential Circuit Test Generation in a Genetic Algorithm Framework,” Proc. Design Automation Conf., 1994, pp. 698–704Google Scholar
  10. [ScMu94]
    D. Schlierkamp-Voosen, H. Mühlenbein, “Strategy Adaptation by Competing Subpopulations,” Proc. Int. Conf. on Parallel Problem Solving from Nature, 1994, pp. 199–208Google Scholar
  11. [SSAb92]
    D.G. Saab, Y.G. Saab, J. Abraham, “CRIS: A Test Cultivation Program for Sequential VLSI Circuits,” Proc. Int. Conf. on Computer Aided Design, 1992, pp. 216–219Google Scholar

Copyright information

© Springer-Verlag 1996

Authors and Affiliations

  • Fulvio Corno
    • 1
  • Paolo Prinetto
    • 1
  • Maurizio Rebaudengo
    • 1
  • Matteo Sonza Reorda
    • 1
  1. 1.Dip. di Automatica e InformaticaPolitecnico di TorinoTorinoItaly

Personalised recommendations