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Experiences in embedded scheduling

  • David M. Jackson
Session 7a: Model Checking (1)
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1051)

Abstract

This paper summarises a number of features of several recent projects in the field of high-integrity embedded system design, and in particular in the design and verification of schedulers and schedules for such systems. It discusses the technical issues of modelling the timing requirements and features of such software with reference to the CSP language and the FDR model checking tool, and makes some observations about the choice and availability of data, re-use of modelling effort, and presentation of results. The technical work is illustrated by a small example, and shows a variety of useful modelling idioms rather than new mathematical results. The final section discusses the applicability of the present process, and attempts to draw conclusions regarding the wider application of formal methods.

Keywords

Embed System Task Execution Minor Cycle Communicate Sequential Process Execution Rate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • David M. Jackson
    • 1
    • 2
  1. 1.Formal Systems Design & Development, Inc.AuburnUSA
  2. 2.Formal Systems (Europe) LtdOxfordUK

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