A miss history-based architecture for cache prefetching

Abstract

This paper describes a hardware controlled cache prefetching technique which uses the past behavior of misses to prefetch. We present a low cost prefetch-on-miss architecture for implementing the prefetcher. Its requirements are (1) less than 6.25% increase in the main memory size, and (2) a bidirectional address bus. We evaluate the performance of our prefetcher using trace driven simulations of ATUM and SPEC benchmark suits. For a 4-way set associative 32KB cache, with at most one prefetch on a miss, we obtain miss ratio improvements over a non-prefetching scheme in the range of 23 to 37%. This improvement is obtained at the cost of increasing the bus traffic up to 39% above the non-prefetching scheme. In comparison to the sequential method, the miss ratio improves up to 14% and the bus traffic reduces up to 17%. Similar improvements over the sequential technique are obtained for larger caches and direct mapped caches.