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A VLSI scalable processor array for motion estimation

  • P. Baglietto
  • M. Maresca
  • A. Migliaro
  • M. Migliardi
Software and Hardware Architectures for Image Processing
Part of the Lecture Notes in Computer Science book series (LNCS, volume 974)

Abstract

In this paper we describe a parallel architecture for motion estimation based on the Full Search Block Matching Algorithm. The distinctive characteristic of the proposed architecture is its suitability to be implemented both in a high performance dedicated device for embedded systems (e.g. an ASIC) and on mesh connected SIMD massively parallel computers. The paper describes the first of these options in detail.

Keywords

MPEG Motion Estimation Processor Array VLSI 

References

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    Video codec for audio visual services at px 64 kb/s, CC9TT Reccomendation H.261, 1990.Google Scholar
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    Coding of moving pictures and associated audio, Committee Draft of standard ISO11172: ISO/MPEG/90/176, Dec. 1991.Google Scholar
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    P. Ruetz, P. Tong, D. Bailey, D. Luthi and P. Ang, A high performance full-motion video compression chip set, IEEE Trans. on Circuits and systems for video technology, Vol. 2, N. 2, June 1992, pp. 111–122.Google Scholar
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    H. Fujiwara, M. Liou, M. Sun, K. Yang, M. Maruyama, K. Shomura and K. Ohyama, An all-ASIC implementation of a low bit-rate video codec, IEEE Trans. on Circuits and systems for video technology, Vol. 2, N. 2, June 1992, pp. 123–134.Google Scholar
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    C. Hsieh and T. Lin, VLSI architecture for block-matching motion estimation algorithm, IEEE Trans. on Circuits and systems for video technology, Vol. 2, N. 2, June 1992, pp. 169–175.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1995

Authors and Affiliations

  • P. Baglietto
    • 1
  • M. Maresca
    • 1
  • A. Migliaro
    • 1
  • M. Migliardi
    • 1
  1. 1.DISTUniversity of GenoaGenova

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