Abstract
We developed a telecommunication-oriented LUT-based FPGA and its dedicated CAD system. The FPGA, called PROTEUS, has some unique features. For example, its logic block structure enables the user to easily realize the basic components used in telecommunication circuits such as binary counters and pattern matching circuits. In addition, PROTEUS has a lot of regularly-placed latches to accomplish pipelined data processing. With a logic synthesis system, the CAD system offers a top-down design methodology. The programming data downloaded into PROTEUS can be obtained directly from RTL language descriptions. Furthermore, the CAD system supports hardware-macro-based design to realize high performance circuits. In this paper, we introduce the PROTEUS FPGA architecture and CAD system. In addition, we show some experimental results proving that PROTEUS is applicable to real telecommunication circuits.
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References
Stallings W., “Advances in ISDN and Broadband ISDN,” IEEE Computer Society Press, 1992.
Ohta N., Nakada H., Yamada K., Tsutsui A., and Miyazaki T., “PROTEUS: Programmable Hardware for Telecommunication Systems,” IEEE Proc. ICCD'94, pp. 178–183, October 1994.
Nakamura Y., Oguri K., Nagoya A., and Nomura R., “A Hierarchical Behavioral Description Based CAD System,” Proc. EURO ASIC, 1990.
Brown S.D., Francis R.J., Rose J. and Vranesic Z.G., “Field-Programmable Gate Arrays,” Kluwer Academic Publishers, 1992.
I-Cube, Inc., “The FPID Family Data Sheet,” April 1994.
Aptix Corporation, “Data Book,” February 1993.
Kirkoatrick S., Gelatt J.C.D., and Vecchi M., “Optimization by simulated annealing,” SCIENCE, Vol. 220, pp. 671–679, May 1983.
Ohta. N., Yamada K., Tsutsui A. and Nakada H., “New Application of FPGAs to Programmable Digital Communication Circuits,” Proc. FPL'92, September 1992.
Leiserson C.E., Rose F.M. and Saxe J.B., “Retiming Synchronous Circuitry,” Algorithmica, Vol.6, pp. 5–35, 1991.
Nakada H., Yamada K., Tsutsui A., and Ohta N., “A Design Method for Realising Real-time Circuits on Multiple-FPGA Systems,” in More FPGA, Moore W. R. and Luk W. eds. (Proc. FPL'93), pp.129–137, 1994.
Miyazaki T., Nakada H., Tsutsui T., Yamada K., and Ohta N., “A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs,” Proc. FPL'94, pp.89–98, September 1994.
Xilinx Inc., “The Field Programmable Gate Array Data Book,” 1994.
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© 1995 Springer-Verlag Berlin Heidelberg
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Miyazaki, T., Yamada, K., Tsutsui, A., Nakada, H., Ohta, N. (1995). Telecommunication-oriented FPGA and dedicated CAD system. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_98
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DOI: https://doi.org/10.1007/3-540-60294-1_98
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